Queue depth management for host systems accessing a peripheral component interconnect express (PCIe) device via a PCIe switch

Patent metadata

Field	Value
Publication number	US-10877913-B2
Application number	US-202016741667-A
Country	US
Kind code	B2
Filing date	Jan 13, 2020
Priority date	Jun 28, 2017
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment involve a host system configured to maintain quality of service statistics corresponding to data interactions with a PCIe storage device available via a PCIe switch. The host system may further receive secondary quality of service statistics for one or more other host systems communicatively coupled to the PCIe device via the PCIe switch, and determine a maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain a quality of service for at least the host system.

First claim

What is claimed is:

1. A host system comprising:
one or more non-transitory computer-readable storage media;
a processing system operatively coupled to the one or more non-transitory computer-readable storage media; and
program instructions stored on the one or more non-transitory computer-readable storage media to manage a maximum queue depth for the host system for data interactions with a Peripheral Component Interconnect Express (PCIe) device available to the host system via a PCIe switch which, when read and executed by the processing system of the host system, direct the processing system to:
maintain at the host system quality of service statistics for data interactions between the host system and the PCIe device;
receive at the host system second quality of service statistics for data interactions of one or more other host systems communicatively coupled to the PCIe device via the PCIe switch; and
determine at the host system the maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain at least a minimum quality of service for the host system.

2. The host system of claim 1 , wherein the program instructions further direct the processing system to provide the quality of service statistics to the PCIe switch for forwarding to the one or more other host systems.

3. The host system of claim 2 , wherein providing the quality of service statistics to the PCIe switch comprises:
receiving a request for the quality of service statistics from the PCIe switch; and
in response to the request, providing the quality of service statistics to the PCIe switch.

4. The host system of claim 1 , wherein the quality of service statistics comprise one or more of latency information for data requests to the PCIe device, input/output operations per second (IOPS) with the PCIe device, and an amount of bytes communicated over a time period with the PCIe device.

5. The host system of claim 1 , wherein the minimum quality of service for the host system comprises a maximum latency and an expected block request size.

6. The host system of claim 1 , wherein the minimum quality of service for the host system comprises an administrator-defined minimum quality of service for data interactions with the PCIe device.

7. The host system of claim 1 , wherein the program instructions further direct the processing system to:
after determining the maximum queue depth, receive third quality of service statistics for data interactions of the one or more other host systems with the PCIe device; and
determine a second maximum queue depth based on the quality of service statistics and the third quality of service statistics to maintain at least the minimum quality of service for the host system.

8. The host system of claim 1 , wherein the PCIe device comprises a PCIe storage device.

9. The host system of claim 1 , wherein the PCIe device comprises a Non-Volatile Memory express (NVMe) storage device.

10. A system comprising:
a first host system;
one or more secondary host systems; and
a Peripheral Component Interconnect Express (PCIe) switch coupled to the first host system and the one or more secondary host systems, wherein the PCIe switch provides connectivity for the first host system and the one or more secondary host systems to a PCIe device;
wherein the first host system is configured to:
maintain quality of service statistics for data interactions between the first host system and the PCIe device;
receive second quality of service statistics from the PCIe switch for data interactions of the one or more secondary host systems with the PCIe device; and
determine a maximum queue depth for data interactions between the first host system and the PCIe device based on the quality of service statistics and the second quality of service statistics to maintain at least a minimum quality of service for the first host system.

11. The system of claim 10 , wherein the PCIe switch is configured to:
obtain the quality of service statistics from the first host system; and
distribute the quality of service statistics to the one or more secondary host systems.

12. The system of claim 10 , wherein obtaining the quality of service statistics from the first host system comprises reading the quality of service statistics from a memory location of the first host system.

13. The system of claim 10 , wherein the quality of service statistics comprise one or more of latency information for data requests to the PCIe device, input/output operations per second (IOPS) with the PCIe device, and an amount of bytes communicated over a time period with the PCIe device.

14. The system of claim 10 , wherein the minimum quality of service for the first host system comprises a maximum latency for data interactions with the PCIe device.

15. The system of claim 10 , wherein the minimum quality of service for the first host system comprises an administrator-defined minimum quality of service for data interactions with the PCIe device.

16. The system of claim 10 , wherein the first host system is further configured to:
after determining the maximum queue depth, receive third quality of service statistics from the PCIe switch for data interactions of the one or more secondary host systems with the PCIe device; and
determine a second maximum queue depth for data interactions between the first host system and the PCIe device based on the quality of service statistics and the third quality of service statistics to maintain at least the minimum quality of service for the first host system.

17. The system of claim 10 , wherein the PCIe device comprises a PCIe storage device.

18. The system of claim 10 , wherein the PCIe device comprises a Non-Volatile Memory express (NVMe) storage device.

19. The system of claim 10 , further comprising the PCIe device.

20. A host system comprising:
control means for managing a maximum queue depth for the host system for data interactions with a Peripheral Component Interconnect Express (PCIe) device available to the host system via a PCIe switch, the control means of the host system comprising:
means for maintaining quality of service statistics for data interactions between the host system and the PCIe device;
means for receiving second quality of service statistics for data interactions of one or more other host systems communicatively coupled to the PCIe device via the PCIe switch; and
means for determining the maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain at least a minimum quality of service for the host system.

Assignees

• Western Digital Tech Inc

Inventors

• Elkington Susan
• Roberson Randy
• Hess Randall
• Stillwell Michael
• Walker Michael

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F13/161

  with latency improvement · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title