Vector galois field multiply sum and accumulate instruction

Patent metadata

Field	Value
Publication number	US-10877753-B2
Application number	US-201816170577-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Jan 23, 2013
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and exclusively ORed with a corresponding element of a fourth operand of the instruction. The results are placed in a selected operand.

First claim

What is claimed is:

1. A computer program product for executing a machine instruction, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processor and storing instructions for performing a method comprising:
obtaining the machine instruction for execution, the machine instruction having associated therewith:
an opcode identifying a Vector Galois Field Multiply Sum and Accumulate operation; and
a plurality of operands including a first operand, a second operand, a third operand, and a fourth operand, wherein two operands of the plurality of operands include a size of elements that are double size of elements of two other operands of the plurality of operands; and

executing the machine instruction, the executing comprising:
multiplying one or more elements of the second operand with one or more elements of the third operand using carryless multiplication to obtain a plurality of products;
performing a first mathematical operation on the plurality of products to obtain a first result;
performing a second mathematical operation on the first result and one or more selected elements of the fourth operand to obtain a second result; and
placing the second result in the first operand.

2. The computer program product of claim 1 , wherein the multiplying comprises multiplying each element of the second operand with a corresponding element of the third operand using carryless multiplication resulting in even-odd pairs of double element-sized products.

3. The computer program product of claim 2 , wherein the carryless multiplication has an order of two.

4. The computer program product of claim 2 , wherein the first mathematical operation comprises an exclusive OR operation, and wherein the even-odd pairs of double element-sized products are exclusive ORed with each other to obtain the first result.

5. The computer program product of claim 4 , wherein the second mathematical operation comprises an exclusive OR operation, and wherein the first result is exclusive ORed with a corresponding double-wide element of the fourth operand to obtain the second result.

6. The computer program product of claim 5 , wherein the placing comprises placing the second result in a double-wide element of the first operand.

7. The computer program product of claim 1 , wherein the machine instruction further has associated therewith a control to specify a size of elements of the second operand and the third operand.

8. The computer program product of claim 7 , wherein the two operands of the plurality of operands that include the size of elements that are double size are the first operand and the fourth operand, and the two other operands of the plurality of operands are the second operand and the third operand.

9. The computer program product of claim 1 , wherein the two operands of the plurality of operands that include the size of elements that are double size are the first operand and the fourth operand, and the two other operands of the plurality of operands are the second operand and the third operand.

10. The computer program product of claim 1 , wherein the machine instruction has associated therewith an extension field to be used in designating one or more registers, and wherein a first register field of the machine instruction is combined with a first portion of the extension field to designate a first register, the first register to be used to provide the first operand, a second register field is combined with a second portion of the extension field to designate a second register, the second register to be used to provide the second operand, a third register field is combined with a third portion of the extension field to designate a third register, the third register to be used to provide the third operand, and a fourth register field is combined with a fourth portion of the extension field to designate a fourth register, the fourth register to be used to provide the fourth operand.

11. A computer system for executing a machine, the computer system comprising:
a memory; and
a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining the machine instruction for execution, the machine instruction having associated therewith:
an opcode identifying a Vector Galois Field Multiply Sum and Accumulate operation; and
a plurality of operands including a first operand, a second operand, a third operand, and a fourth operand, wherein two operands of the plurality of operands include a size of elements that are double size of elements of two other operands of the plurality of operands; and

executing the machine instruction, the executing comprising:
multiplying one or more elements of the second operand with one or more elements of the third operand using carryless multiplication to obtain a plurality of products;
performing a first mathematical operation on the plurality of products to obtain a first result;
performing a second mathematical operation on the first result and one or more selected elements of the fourth operand to obtain a second result; and
placing the second result in the first operand.

12. The computer system of claim 11 , wherein the multiplying comprises multiplying each element of the second operand with a corresponding element of the third operand using carryless multiplication resulting in even-odd pairs of double element-sized products.

13. The computer system of claim 12 , wherein the carryless multiplication has an order of two.

14. The computer system of claim 12 , wherein the first mathematical operation comprises an exclusive OR operation, and wherein the even-odd pairs of double element-sized products are exclusive ORed with each other to obtain the first result.

15. The computer system of claim 14 , wherein the second mathematical operation comprises an exclusive OR operation, and wherein the first result is exclusive ORed with a corresponding double-wide element of the fourth operand to obtain the second result.

16. The computer system of claim 15 , wherein the placing comprises placing the second result in a double-wide element of the first operand.

17. The computer system of claim 11 , wherein the machine instruction further has associated therewith a control to specify a size of elements of the second operand and the third operand.

18. The computer system of claim 17 , wherein the two operands of the plurality of operands that include the size of elements that are double size are the first operand and the fourth operand, and the two other operands of the plurality of operands are the second operand and the third operand.

19. The computer system of claim 11 , wherein the two operands of the plurality of operands that include the size of elements that are double size are the first operand and the fourth operand, and the two other operands of the plurality of operands are the second operand and the third operand.

20. The computer system of claim 11 , wherein the machine instruction has associated therewith an extension field to be used in designating one or more registers, and wherein a first register field of the machine instruction is combined with a first portion of the extension field to designate a first register, the first register to be used to provide the first operand, a second register field is combined with a second portion of the extension field to designate a second register, the second register to be used to provide the second operand, a third register fie

Assignees

• IBM

Inventors

• Bradbury Jonathan D

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/30149

  of variable length instructions · CPC title

• G06F7/498

  using counter-type accumulators · CPC title