Segment divider, segment division operation method, and electronic device

Patent metadata

Field	Value
Publication number	US-10877733-B2
Application number	US-201815993906-A
Country	US
Kind code	B2
Filing date	May 31, 2018
Priority date	Nov 14, 2017
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A segment divider, a segment division operation method, and an electronic device are disclosed, relating to the technical field of digital signal processing. The divider includes: a first shift register circuit; a second shift register circuit; a calculation circuit configured to compare data in first registers and data in second registers according to the cascade order, to perform a preset operation and generate an operation result; a third shift register circuit configured to receive and register the operation result bit by bit; then a shift control circuit configured to control the first shift register circuit and the third shift register circuit to perform a shift operation; a counting circuit configured to accumulate the number of shift operations after each shift operation, and send an output signal to finish the operation or send a calculation signal to continue the operation; and an output circuit configured to output a target result.

First claim

What is claimed is:

1. A segment divider comprising:
a first shift register circuit, comprising a plurality of cascaded first registers and configured to receive data of a dividend bit by bit;
a second shift register circuit, comprising a plurality of cascaded second registers and configured to receive and store data of a divisor;
a calculation circuit, comprising a plurality of cascaded calculators, the calculator being configured to compare the registered data in the first register and the registered data in the second register according to the cascade order, to perform a preset operation and to generate an operation result according the comparison result;
a third shift register circuit, comprising a plurality of cascaded third registers and configured to receive and register the operation result bit by bit;
a shift control circuit, configured to control the first shift register circuit and the third shift register circuit to perform a shift operation after each operation result is generated;
a counting circuit, configured to accumulate a number of the shift operation after each shift operation, and when a result of the accumulation equals a target number of bits, to send an output signal, and when the result of the accumulation is not equal to the target number of bits, to send a calculation signal to the calculation circuit to continue the operation; and
an output circuit, configured to receive the output signal to finish the operation, and to output a target result, wherein the target result comprises a quotient, and the quotient is the data registered in the third shift register circuit when the output signal is received,
wherein the calculator comprises:
a comparator, configured to compare the registered data in each stage of the first registers and the registered data in each stage of the second registers according to the cascade order; and
a subtractor, configured to perform a subtraction operation on the registered data in all of the first registers and the registered data in all of the second registers when the registered data in the first register circuit is larger than the registered data in the second register circuit, and to replace the registered data in the first registers with a difference resulted from the subtraction operation, and meanwhile to add one to a lowest bit of the third shift register circuit as the operation result;
wherein when the registered data in the first register circuit is smaller than the registered data in the second register circuit, filling zero to the lowest bit of the third shift register circuit as the operation result.

2. The segment divider according to claim 1 , wherein the first registers, the second registers, and the calculators are same in number, and the first registers and the second registers are same in bit width.

3. The segment divider according to claim 2 , wherein a number of the second registers is N, where N=┌number of bits of the data of the divisor/bit width of the second register┐, and ┌ ┐ is a round up function.

4. The segment divider according to claim 3 , wherein when the target number of bits is equal to the number of bits of the data of the dividend, the target result further comprises a remainder, and the remainder is registered data in the first shift register circuit when the output signal is received.

5. The sectional divider according to claim 1 , wherein the comparing the registered data in the first registers and the registered data in the second registers according to the cascade order comprises:
for the first registers and the second registers at stages higher than a lowest stage, when the registered data in the first register is equal to the registered data in the second register, comparing, by the comparator of a next lower stage, the registered data in the first register of a next lower stage and the registered data in the second register of a next lower stage.

6. The segment divider according to claim 1 , wherein the first shift register circuit further comprises:
a buffer, connected to a front end of the first register and configured to receive the data of the dividend and to output data to the first register bit by bit during the operation;
wherein when the first register receives the data from the buffer, the first register at a highest stage discards data at a highest bit, and the buffer fills with a zero at a lowest bit after the buffer outputs data to the first register.

7. The segment divider according to claim 6 , wherein the buffer comprises a plurality of cascaded buffer registers, and a sum of the bit widths of all the buffer registers is equal to a number of bits of the data of the dividend.

8. The segment divider according to claim 7 , wherein the shift control circuit is configured to control the buffer registers, the first registers, and the third registers to perform a left shift operation.

9. The segment divider according to claim 1 , further comprising a sign control circuit connected to the output circuit;
wherein the sign control circuit comprises:
a first sign storing subcircuit, configured to store a sign of the dividend;
a second sign storing subcircuit, configured to store a sign of the divisor; and
a sign output subcircuit, configured to perform a bit XOR operation on the sign of the dividend and the sign of the divisor, to obtain a sign of the quotient.

10. The segment divider according to claim 1 , further comprising:
an enabling circuit, configured to control the calculation circuit to start working;
an end circuit, configured to mark that the segment divider has finished the working;
a reset circuit, configured to reset the circuits of the segment divider; and
a clock circuit, configured to provide a clock signal to the segment divider.

11. A segment division operation method, applied to a segment divider, wherein the segment divider comprises:
a first shift register circuit, comprising a plurality of cascaded first registers and configured to receive data of a dividend bit by bit;
a second shift register circuit, comprising a plurality of cascaded second registers and configured to receive and store data of a divisor;
a calculation circuit, comprising a plurality of cascaded calculators, the calculator being configured to compare the registered data in the first register and the registered data in the second register according to the cascade order, to perform a preset operation and generate an operation result according the comparison result;
a third shift register circuit, comprising a plurality of cascaded third registers and configured to receive and register the operation result bit by bit;
a shift control circuit, configured to control the first shift register circuit and the third shift register circuit to perform a shift operation after each operation result is generated;
a counting circuit, configured to accumulate a number of the shift operation after each shift operation, and when a result of the accumulation equals a target number of bits, to send an output signal, and when the result of the accumulation is not equal to the target number of bits, to send a calculation signal to the calculation circuit to continue the operation; and
an output circuit, configured to receive the output signal to finish the operation, and to output a target result, wherein the target result comprises a quotient, and the quotient is the data registered in the third shift register circuit when the output signal is received, and
wherein the calculator comprises:
a comparator, configured to compare the registered data in each stage of the first registers and the registered data in each stage of the second registers according to the cascade order; and
a subtractor,

Assignees

• Boe Technology Group Co Ltd

Inventors

• Gao Yang

Classifications

• G06F7/535 Primary

  Dividing only · CPC title

• G06F7/02

  Comparing digital values (G06F7/06, {G06F7/22,} G06F7/38 take precedence) · CPC title

• G06F7/537 Primary

  Reduction of the number of iteration steps or stages, e.g. using the Sweeny-Robertson-Tocher [SRT] algorithm · CPC title

• G06F7/72 Primary

  using residue arithmetic · CPC title