Context switches with processor performance states

Patent metadata

Field	Value
Publication number	US-10877548-B2
Application number	US-201815916894-A
Country	US
Kind code	B2
Filing date	Mar 9, 2018
Priority date	Mar 9, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

In example implementations, an apparatus is provided. The apparatus includes a context switch block, a processor performance state block, and a task execution block. The context switch block is to perform a context switch. The processor performance state block is to load a processor with a processor performance state stored in a context information associated with a task. The task execution block is to execute the task with the processor operating at the processor performance state loaded from the context information.

First claim

The invention claimed is:

1. A computer system, comprising:
a processor;
a context switch controller module coupled to the processor and configured to perform context switching in association with the processor, during which the processor is configured to switch from execution of a first task to execution of a second task;
a memory device coupled to the processor and configured to store a set of context information corresponding to the second task, wherein the context information is loaded during the context switching to avow the processor to execute the second task, and wherein the context information includes a processor performance state that indicates an operating frequency, an operating voltage, or both for the processor; and
a processor performance state module coupled to the processor and configured to place the processor in the processor performance state included in the context information;
wherein when a power management module coupled to the processor is configured to place the processor, according to a predetermined power-management plan, in a second performance state that is lower than the processor performance state included in the context information, the processor performance state module is further configured to override the power management module by placing the processor in the performance state included in the context information in association with the context switching instead of the performance state indicated by the predetermined power-management plan.

2. The computer system of claim 1 , wherein the context information is stored in at least one of: a random access memory of the apparatus, a non-volatile memory of the processor, an external cache, or an internal cache.

3. The computer system of claim 1 , wherein the context switch controller module is configured to receive a signal to perform a subsequent context switching and to store a current processor performance state with an updated context information in response to the signal to perform the subsequent context switching.

4. The computer system of claim 3 , wherein the current processor performance state is modified externally by a power management device executing power management software.

5. A computer-executed method, comprising:
receiving, by a processor, an indication to perform context switching, during which the processor is configured to switch from execution of a first task to execution of a second task;
storing, by a memory device, a set of context information corresponding to the second task, wherein the context information is loaded during the context switching to allow the processor to execute the second task, and wherein the context information includes a processor performance state that indicates an operating frequency, an operating voltage, or both for the processor;
reading, by the processor, from the memory device, the processor performance state included in the context information associated with the second task;
changing, by the processor, operation of the processor to the processor performance state included in the context information associated with the second task;
executing, by the processor, the second task while operating the processor at the processor performance state; and
in response to determining, by the processor, that a power management module places the processor, according to a predetermined power-management plan, in a second performance state that is lower than the processor performance state included in the context information, overriding the power management module by placing the processor in the performance state included in the context information associated with the second task instead of the second performance state indicated by the predetermined power-management plan.

6. The method of claim 5 , wherein the indication to perform the context switching is received from a virtual machine manager.

7. The method of claim 5 , wherein the changing is performed before the context switching occurs.

8. The method of claim 5 , further comprising:
receiving, by the processor, an indication to perform a subsequent context switching and execute a different task;
storing, by the processor, a current processor performance state with an updated context information in response to the indication to perform the subsequent context switching.

9. The method of claim 8 , further comprising:
receiving, by the processor, an instruction to modify the current processor performance state to a desired processor performance state.

10. The method of claim 8 , wherein the updated context information is stored in at least one of: a random access memory of the apparatus, a non-volatile memory of the processor, an external cache, and internal cache.

11. A non-transitory computer readable storage medium encoded with instructions executable by a processor, the non-transitory computer-readable storage medium comprising:
instructions to execute a first task while operating the processor at a processor performance level associated with the first task;
instructions to perform context switching, during which the processor is configured to switch from execution of the first task to execution of a second task;
instructions to store a set of context information corresponding to the second task, wherein the context information is loaded during the context switching to allow the processor to execute the second task, wherein the context information includes a processor performance level that indicates an operating frequency, an operating voltage, or both for the processor, wherein the context information is to provide the processor performance level to a different processor that executes the second task;
instructions to load the processor performance level included in the context information associated with the second task;
instructions to execute the second task at the processor performance level included in the context information; and
instructions to, in response to determining, by the processor, that a power management module places the processor, according to a predetermined power-management plan, in a second performance level that is lower than the processor performance level included in the context information, override the power management module by placing the processor in the performance level included in the context information associated with the second task instead of the second performance state indicated by the predetermined power-management plan.

12. The non-transitory computer readable storage medium of claim 11 , wherein the context information is stored in at least one of: a random access memory of the apparatus, a non-volatile memory of the processor, an external cache, or an internal cache.

13. The non-transitory computer readable storage medium of claim 11 , wherein computing resources of the processor and the different processor are shared as part of a virtualized machine.

14. The non-transitory computer readable storage medium of claim 11 , further comprising:
instructions to modify the processor performance level.

15. The non-transitory computer readable storage medium of claim 11 , further comprising:
instructions to predict the context switching to the second task; and
instructions to load the processor performance level before the context switching is performed.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Faasse Scott

Classifications

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F9/463

  Program control block organisation · CPC title