Semiconductor wafer testing system and related method for improving external magnetic field wafer testing

Patent metadata

Field	Value
Publication number	US-10877089-B2
Application number	US-201916411647-A
Country	US
Kind code	B2
Filing date	May 14, 2019
Priority date	Sep 24, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

First claim

What is claimed is:

1. A semiconductor wafer testing system, comprising:
a semiconductor wafer prober comprising one or more conductive probes, wherein the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer; and
a ferromagnetic wafer chuck, wherein the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the semiconductor wafer prober positions the one or more conductive probes on the IC; and
an upper magnet disposed over the ferromagnetic wafer chuck, wherein the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and wherein the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

2. The semiconductor wafer testing system of claim 1 , wherein the upper magnet is an electromagnet.

3. The semiconductor wafer testing system of claim 1 , wherein the ferromagnetic wafer chuck is a temporary magnet.

4. The semiconductor wafer testing system of claim 1 , wherein the external magnetic field passes through the IC while the one or more conductive probes are positioned on the IC, and wherein the amplified magnetic field strength is between about 0.01 tesla and about 1 tesla.

5. The semiconductor wafer testing system of claim 1 , further comprising:
a wafer probing housing, wherein the ferromagnetic wafer chuck is disposed in the wafer probing housing, and wherein the upper magnet is disposed over the wafer probing housing.

6. The semiconductor wafer testing system of claim 1 , wherein a composition of the ferromagnetic wafer chuck comprises about 99.9% of a ferromagnetic material.

7. The semiconductor wafer testing system of claim 6 , wherein the ferromagnetic material is iron, cobalt, or nickel.

8. A method comprising:
providing a semiconductor wafer comprising an integrated chip (IC) to a semiconductor wafer testing system, wherein the semiconductor wafer testing system comprises an upper magnet disposed over a ferromagnetic wafer chuck, and wherein the semiconductor wafer testing system comprises a semiconductor wafer prober comprising one or more conductive probes;
positioning the semiconductor wafer on the ferromagnetic wafer chuck;
positioning the one or more conductive probes on the IC;
generating an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, wherein the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength;
providing an IC testing signal to the IC via the one or more conductive probes; and
receiving an IC output signal based on the IC testing signal via the one or more conductive probes to determine performance characteristics of the IC.

9. The method of claim 8 , wherein the amplified magnetic field strength is greater than about 0.01 tesla.

10. The method of claim 8 , further comprising:
before the external magnetic field is generated, providing a write current to the IC via the one or more conductive probes to set a resistive state of a magnetic tunnel junction (MTJ) to a first resistive state, wherein the MTJ is configured to switch between the first resistive state and a second resistive state different than the first resistive state;
after the external magnetic field is generated, providing the IC testing signal to the MTJ to probe the resistive state of the MTJ; and
comparing the IC output signal to a threshold output signal to determine if the external magnetic field switched the resistive state of the MTJ from the first resistive state to the second resistive state.

11. The method of claim 10 , wherein the performance characteristics of the IC comprise a maximum external magnetic field strength, and wherein the resistive state of the MTJ switches from the first resistive state to the second resistive state at or above the maximum external magnetic field strength.

12. The method of claim 11 , further comprising:
performing a first instance of a magnetic field strength sweep to determine the maximum external magnetic field strength, wherein the magnetic field strength sweep comprises:
increasing the magnetic field strength of the external magnetic field at predefined intervals from a lower magnetic field strength to an upper magnetic field strength;
providing a series of IC testing signals to the MTJ to probe the resistive state of the MTJ at each of the intervals;
receiving a series of IC output signals corresponding to the IC testing signals; and
comparing each of the IC output signals of the series of IC output signals to the threshold output signal to determine the resistive state of the MTJ at each of the intervals.

13. The method of claim 12 , further comprising:
while the first instance of the magnetic field strength sweep is being performed, heating the IC to a first predefined testing temperature;
performing a second instance of the magnetic field strength sweep; and
while the second instance of the magnetic field strength sweep is being performed, heating the IC to a second predefined testing temperature different than the first predefined testing temperature.

14. The method of claim 13 , wherein the performance characteristics of the IC comprise:
a first temperature related maximum external magnetic field strength, wherein the resistive state of the MTJ switches from the first resistive state to the second resistive state at or above the first temperature related maximum external magnetic field strength when the IC is at the first predefined testing temperature; and
a second temperature related maximum external magnetic field strength, wherein the resistive state of the MTJ switches from the first resistive state to the second resistive state at or above the second temperature related maximum external magnetic field strength when the IC is at the second predefined testing temperature.

15. The method of claim 14 , wherein the lower magnetic field strength is about 0.01 tesla and the upper magnetic field strength is about 1 tesla.

16. The method of claim 15 , wherein the first predefined testing temperature and the second predefined testing temperature are between about 0° C. and about 150° C.

17. A method comprising:
positioning a semiconductor wafer comprising an integrated chip (IC) on a ferromagnetic wafer chuck, wherein the IC comprises a magnetic tunnel junction (MTJ), and wherein the MTJ is configured to switch between a first resistive state and a second resistive state;
providing a prober positioning electrical signal to a wafer prober controller, wherein the wafer prober controller positions one or more conductive probes on the IC based on the prober positioning electrical signal;
providing a write current to the IC via the one or more conductive probes to set a resistive state of the MTJ to the first resistive state;
while the one or more conductive probes are positioned on the IC, providing a first magnetic field testing signal to an upper magnet disposed directly over the ferromagnetic wafer chuck to generate a first external magnetic field between the upper magnet and the ferromagnetic wafer chuck, wherein the first external magnetic field passes through the IC in a first direction;
after the first external magnetic field is generated:
providing a first testing input electrical signal to the IC via the one or more conductive probes to probe the resistive

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry-Hak-Lay
• Chang Chih-Yang
• Wang Ching-Huang
• Chiang Tien-Wei
• Shih Meng-Chun
• Wang Chia Yu

Classifications

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C29/56016 Primary

  Apparatus features · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G01R31/2891

  related to sensing or controlling of force, position, temperature (G01R31/2874 takes precedence; sensing of force G01L; sensing of position G01B, G01D; sensing of temperature G01K; controlling in general G05) · CPC title

• G11C2029/5602

  Interface to device under test · CPC title