Voltage follower circuit

Patent metadata

Field	Value
Publication number	US-10873305-B2
Application number	US-201916292603-A
Country	US
Kind code	B2
Filing date	Mar 5, 2019
Priority date	Sep 13, 2018
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A voltage follower circuit according to an embodiment includes first and second paths, the first path includes a first nMOS transistor and a first pMOS transistor, the second path includes a second nMOS transistor and a second pMOS transistor, an input voltage is supplied to the gate of the first nMOS transistor, an output voltage is supplied to the gate of the second nMOS transistor, a voltage lower than the output voltage is supplied to the gate of the first pMOS transistor, and a voltage lower than the input voltage is supplied to the gate of the second pMOS transistor.

First claim

What is claimed is:

1. A voltage follower circuit comprising a first path for a first differential current and a second path for a second differential current, wherein
the first path includes a first nMOS transistor having a drain connected to a predetermined potential and a gate supplied with an input voltage, and a first pMOS transistor having a drain connected to a potential lower than the predetermined potential,
the second path includes a second nMOS transistor having a drain connected to the predetermined potential and a gate supplied with an output voltage, and a second pMOS transistor having a drain connected to a potential lower than the predetermined potential,
the first pMOS transistor has a gate to which a first voltage lower than the output voltage is supplied, and
the second pMOS transistor has a gate to which a second voltage lower than the input voltage is supplied, and wherein
the voltage follower circuit further comprises a capacitor having one end connected to the gate of the first pMOS transistor and another end connected to an output terminal of the output voltage, the capacitor being configured to vary a gate voltage of the first pMOS transistor depending on the output voltage.

2. The voltage follower circuit according to claim 1 , wherein a differential nMOS transistor is configured by the first nMOS transistor and the second nMOS transistor, and a differential pMOS transistor is configured by the first pMOS transistor and the second pMOS transistor.

3. The voltage follower circuit according to claim 1 , wherein
a source of the first nMOS transistor and a source of the first pMOS transistor are connected to each other to configure the first path, and
a source of the second nMOS transistor and a source of the second pMOS transistor are connected to each other to configure the second path.

4. The voltage follower circuit according to claim 1 , wherein the first differential current is set by a gate-source voltage of the first pMOS transistor, and the second differential current is set by a gate-source voltage of the second pMOS transistor.

5. The voltage follower circuit according to claim 1 , further comprising a first generating circuit for generating the first voltage, and a second generating circuit for generating the second voltage.

6. The voltage follower circuit according to claim 4 , wherein
the second generating circuit includes a third nMOS transistor and a third pMOS transistor, sources of the third nMOS transistor and the third pMOS transistor being connected to each other,
the third nMOS transistor has a gate to which the input voltage is applied, and a drain connected to the predetermined potential,
the third pMOS transistor has a gate connected to a drain of the third pMOS transistor and the gate of the second pMOS transistor, the drain of the third pMOS transistor being connected to a constant current circuit,
the first generating circuit includes a fourth nMOS transistor and a fourth pMOS transistor, sources of the fourth nMOS transistor and the fourth pMOS transistor being connected to each other,
the fourth nMOS transistor has a gate to which the output voltage is applied, and a drain connected to the predetermined potential, and
the fourth pMOS transistor has a gate connected to a drain of the fourth pMOS transistor and the gate of the first pMOS transistor, the drain of the fourth pMOS transistor being connected to the constant current circuit.

7. The voltage follower circuit according to claim 6 , wherein back gate voltages of the first to fourth nMOS transistors are set to a first midpoint potential, and back gate voltages of the first to fourth pMOS transistors are set to a second midpoint potential.

8. The voltage follower circuit according to claim 1 , further comprising an output buffer connected to the first path or the second path, wherein an output of the output buffer is connected to the gate of the second nMOS transistor.

9. The voltage follower circuit according to claim 8 , wherein
the output buffer includes a fifth pMOS transistor, and
the fifth pMOS transistor has a drain connected to the gate of the second nMOS transistor and the gate of the fourth nMOS transistor.

10. The voltage follower circuit according to claim 8 , wherein
the output buffer includes a fifth nMOS transistor, and
the fifth nMOS transistor has a source connected to the gate of the second nMOS transistor and the gate of the fourth nMOS transistor.

11. The voltage follower circuit according to claim 6 , wherein the constant current circuit has a temperature characteristic of a plus temperature gradient.

12. The voltage follower circuit according to claim 1 , wherein the first and second nMOS transistors or the first and second pMOS transistors operate in a weak inversion region.

13. The voltage follower circuit according to claim 1 , wherein the drain of the first nMOS transistor and the drain of the second nMOS transistor are connected to the predetermined potential via a load circuit.

14. The voltage follower circuit according to claim 1 , wherein a drain of the third pMOS transistor and a drain of the fourth pMOS transistor are connected to a first resistor and a second resistor, respectively.

15. The voltage follower circuit according to claim 6 , further comprising:
a fifth nMOS transistor having a gate connected to the constant current source, a source being grounded, and a drain connected to the drain of the third pMOS transistor; and
a sixth nMOS transistor having a gate connected to the constant current source, a source being grounded, and a drain connected to the drain of the fourth pMOS transistor.

16. The voltage follower circuit according to claim 15 , further comprising:
a seventh nMOS transistor having a gate and a drain that are connected to the constant current source, and a source being grounded; and
an eighth nMOS transistor having a gate connected to the constant current source, a source being grounded, and a drain connected to the output voltage.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Ueda Norihiro

Classifications

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2200/69

  the amplifier stage being a common drain coupled MOSFET, i.e. source follower · CPC title

• H03F2200/513

  the amplifier being made for low supply voltages · CPC title

• H03F1/30

  Modifications of amplifiers to reduce influence of variations of temperature or supply voltage {or other physical parameters (in differential amplifiers H03F3/45479)} · CPC title

• H03F3/505 Primary

  with field-effect devices · CPC title