Three-phase switching unit

Patent metadata

Field	Value
Publication number	US-10873267-B2
Application number	US-201715855288-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Dec 29, 2016
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A three-phase switching unit including three identical switching cells, each including a first switch and a second switch electrically in series, including a substrate having: a first level receiving, on conductive areas, back sides of integrated circuits forming said switches; and at least one second level comprising conductive areas of interconnection of vias between the first and second levels, the conductive areas of the different levels respecting a symmetry of revolution of order 3.

First claim

What is claimed is:

1. A three-phase switching unit including three identical switching cells, each comprising a first switch and a second switch electrically in series, comprising a substrate having:
a first level receiving, on conductive areas, back sides of integrated circuits forming said first switch and said second switch; and
at least one second level comprising conductive areas of interconnection of vias between their first and second levels,
the conductive areas of the different levels respecting a symmetry of revolution of order 3,
wherein the first level comprises:
three first conductive areas of reception of a back-side conduction terminal of at least one first switch of each cell;
three second conductive areas of reception of wires of connection to a front-side conduction terminal of said first switch;
a third central conductive area of reception of a back-side conduction terminal of the second switches of the three cells; and
three fourth conductive areas of reception of wires of connection to a back-side conduction terminal of said second switches.

2. The unit of claim 1 , wherein the second level comprises:
three first conductive areas respectively vertically in line with the first switches; and
at least one second conductive area vertically in line with the second switches.

3. The unit of claim 1 , wherein the second level further comprises three third conductive areas, each connected by vias to a second and to a fourth conductive area of the first level.

4. The unit of claim 1 , wherein said third conductive area of the first level is Y-shaped, each branch receiving one of said second switches.

5. The unit of claim 1 , contained within a triangular shape.

6. The unit of claim 1 , having a third level of its substrate, between the first and second levels, comprising:
first conductive areas vertically in line with each first switch; and
a second conductive area extending under the three second switches.

7. The unit of claim 6 , having a fourth level of its substrate between the second and third levels, comprising:
first conductive areas vertically in line with each first switch; and
a second conductive area extending under the three second switches.

8. The unit of claim 1 , wherein said first switch and said second switch are MOS transistors.

9. The unit of claim 1 , wherein the substrate is a multilevel insulated metal substrate, preferably on ceramic.

10. The unit of claim 1 , wherein the substrate is a multilevel printed circuit.

11. A three-phase current inverter, comprising two units of claim 1 .

12. The inverter of claim 11 , wherein the cells of the two units are electrically connected two by two, the interconnection nodes defining three phase terminals.

13. A three-phase switching unit including three identical switching cells, each comprising a first switch and a second switch electrically in series, comprising a substrate having:
a first level receiving, on conductive areas, back sides of integrated circuits forming said first switch and said second switch; and
at least one second level comprising conductive areas of interconnection of vias between their first and second levels,
the conductive areas of the different levels respecting a symmetry of revolution of order 3,
wherein the first level comprises:
three first conductive areas of reception of a back-side conduction terminal of at least one first switch of each cell;
three second conductive areas of reception of wires of connection to a front-side conduction terminal of said first switch, and wherein the first conductive areas of the first level receive respective conduction terminals of the second switches, the first level further comprising three third conductive areas of reception of wires of connection to respective front-side conduction terminals of the second switches.

14. The unit of claim 13 or claim 2 , wherein the second conductive areas of the first level are each connected, by vias, to one of said first conductive areas of the second level.

15. The unit of claim 13 , wherein said first conductive areas of the second level form a hexagonal ring.

16. The unit of claim 13 , contained within a hexagonal shape.

Assignees

• Commissariat Energie Atomique

Inventors

• Lefevre Guillaume

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title