High performance stacked connector

US10873149B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10873149-B2
Application numberUS-201916388560-A
CountryUS
Kind codeB2
Filing dateApr 18, 2019
Priority dateApr 18, 2018
Publication dateDec 22, 2020
Grant dateDec 22, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A cage for a stacked I/O connector that provides heat dissipation sufficient to support operation of QSFP-DD transceivers with a conventionally-sized cooling fan. The cage includes a second channel, between a first and a third channel that are sized and positioned adjacent ports of a connector so as to receive two transceivers. A face of the second channel may have a pattern of openings that enables a high airflow yet blocks electromagnetic radiation that would otherwise contribute to EMI. An element, adjacent the channel that similarly has a pattern of holes enabling high airflow, may further block EMI.

First claim

Opening claim text (preview).

What is claimed is: 1. A cage assembly for an electrical connector comprising: a first channel defined by conductive walls and configured to receive a transceiver; a second channel defined by conductive walls and adjacent the first channel, the second channel comprising a face comprising a perimeter that bounds an area of the face, the face comprising a plurality of holes therethrough collectively occupying at least 40% of the area of the face; a heat sink disposed in the second channel; and a thermally conductive element extending within the second channel between the face of the second channel and the heat sink, the thermally conductive element comprising a plurality of holes passing therethrough aligned with the plurality of holes of the face of the second channel, wherein: the plurality of holes are arranged in a plurality of lines extending in a first direction; and each of the plurality of lines is offset, in the first direction, from an adjacent line such that holes in the line are disposed between holes of the adjacent line. 2. The cage assembly of claim 1 , wherein: the plurality of lines are separated by a first distance in a second direction, perpendicular to the first direction; the plurality of holes extend in the second direction by at least a second distance; and the first distance is less than the second distance. 3. The cage assembly of claim 1 , wherein: the plurality of lines are separated in a second direction, perpendicular to the first direction, by a first distance; the face has a width in the second direction of less than 20 mm; and the plurality of lines comprises at least 3 lines. 4. The cage assembly of claim 1 , wherein the plurality of holes have perimeters with straight segments. 5. The cage assembly of claim 4 , wherein at least a portion of the plurality of holes comprise hexagons. 6. The cage assembly of claim 1 , wherein the plurality of holes are disposed in a honeycomb pattern. 7. The cage assembly of claim 1 , wherein the plurality of holes collectively occupy an area that is at least 50% of the area of the face. 8. The cage assembly of claim 1 , wherein the plurality of holes collectively occupy an area that is between 50% and 60% of the area of the face. 9. The cage assembly of claim 1 , wherein the first channel is configured to receive a QSFP transceiver. 10. The cage assembly of claim 1 , wherein: the cage further comprises a third channel defined by conductive walls and configured to receive a second transceiver; and the second channel is between the first channel and the third channel. 11. An electronic system comprising: an enclosure having a panel with at least one opening therethrough; a printed circuit board within the enclosure; a cage mounted to the printed circuit board with the connector enclosed by the cage, the cage comprising a first channel, a second channel, and a third channel having ends exposed in the opening, the second channel being disposed between the first channel and the third channel, the end of the second channel comprising a surface comprising a plurality of holes therethrough collectively occupying more than 40% of a surface area of the surface; an electrical connector comprising a first electrical connector port disposed in the first channel and a second electrical connector port disposed in the third channel, the electrical connector being mounted to the printed circuit board; a thermally conductive element disposed within the second channel, the thermally conductive element comprising a plurality of holes passing therethrough aligned with the plurality of holes of the surface of the second; and at least one fan positioned to cause air to flow over the cage, wherein the plurality of holes are disposed in a plurality of rows with the holes in each of the plurality of rows being staggered with respect to holes in an adjacent row such that holes in the row are between holes in the adjacent row in a first direction parallel to the plurality of rows. 12. The electronic system of claim 11 , wherein the plurality of rows are separated by a distance in a second direction perpendicular to the plurality of rows that is less than the dimension of the holes in the second direction. 13. The electronic system of claim 11 , wherein the holes through the thermally conductive element have an aspect ratio of length to diameter of at least 3. 14. The electronic system of claim 11 , wherein the at least one fan is configured to cause a static pressure of less than 1.5 IW (inches of water). 15. A method of operating an electronic system in an ambient environment comprising, within an enclosure, a stacked cage mounted to a printed circuit board comprising stacked first, second and third channels, wherein the second channel has a face at a first end, the method comprising: transmitting or receiving optical signals with a first transceiver consuming between 1 and 15 W, the first transceiver being disposed within the first channel and coupled to a first port of an electrical connector that is mounted to the printed circuit board; transmitting or receiving optical signals with a second transceiver consuming between 1 and 15 W, the second transceiver being disposed within the second channel and coupled to a second port of the electrical connector; flowing air through openings in the face of the second channel that collectively occupy at least 40% of an area of the face and flowing air towards the electrical connector with a fan within the enclosure, thereby dissipating heat from the first transceivers in the first channel and the second transceiver in the third channel at a rate such that a temperature rise of the first and second transceivers relative to an off state of the transceivers is less than 25 degrees C. in an ambient environment of 25 degrees C. 16. The method of claim 15 , wherein: the cage is mounted to a printed circuit board with the first channel adjacent the printed circuit board and the second channel between the first channel and the third channel. 17. The method of claim 15 , wherein: the transceivers in the first and third channels are QSFP-DD transceivers. 18. The method of claim 15 , wherein: the openings in the face are arranged in a honeycomb pattern.

Assignees

Inventors

Classifications

  • G02B6/4268Primary

    Cooling (of instruments G12B15/00; of electric apparatus H05K7/20; of semiconductor devices H10W76/47) · CPC title

  • H01R13/514Primary

    composed as a modular blocks or assembly, i.e. composed of co-operating parts provided with contact members or holding contact members between them · CPC title

  • Transceivers · CPC title

  • Shield structure · CPC title

  • connecting to cables except for flat or ribbon cables · CPC title

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Frequently asked questions

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What does patent US10873149B2 cover?
A cage for a stacked I/O connector that provides heat dissipation sufficient to support operation of QSFP-DD transceivers with a conventionally-sized cooling fan. The cage includes a second channel, between a first and a third channel that are sized and positioned adjacent ports of a connector so as to receive two transceivers. A face of the second channel may have a pattern of openings that en…
Who is the assignee on this patent?
Amphenol Corp
What technology area does this patent fall under?
Primary CPC classification G02B6/4268. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 22 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).