Permanent wafer bonding using metal alloy preform discs

Patent metadata

Field	Value
Publication number	US-10873002-B2
Application number	US-58413506-A
Country	US
Kind code	B2
Filing date	Oct 20, 2006
Priority date	Oct 20, 2006
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A method for fabricating semiconductor devices at the wafer level, and devices fabricated using the method, are described. Wafer-level bonding using a relatively thick layer of electrically conducting bond medium was used to achieve void-free permanent wafer level bonding. The bond medium can be introduced to the pre-bonded wafers by deposition or as a preform. The invention provides a low cost, simple and reliable wafer bonding technology which can be used in a variety of device fabrication processes, including flip chip packaging.

First claim

I claim:

1. A method of wafer-level bonding for fabricating an electronic device, comprising:
forming at least one layer of a first bond medium on a first surface of a first wafer, the first wafer comprising a first material and having a first coefficient of thermal expansion (CTE) and a total thickness variation (TTV) of 1 to 7 microns, the first wafer comprising at least one substrate and a plurality of light-emitting diode (LED) devices, in which the plurality of LED devices are accessible from the first surface;
forming at least one layer of a second bond medium on a second surface of a second wafer, the second wafer comprising a second material dissimilar from said first material and having a second CTE with a thermal mismatch from said first CTE and a TTV of 1 to 7 microns, the second surface comprising a plurality of LED bond areas, wherein the first bond medium and the second bond medium each comprises an electrically conductive material such as at least one metal, a total thickness of the first layer and the second layer being approximately 10 microns or greater, in which the first bond medium and the second bond medium each reduces stress created by said mismatch between said first and second CTEs, wherein the thickness of the first bond medium is different than the thickness of the second bond medium by at least one micron;
aligning the plurality of LED devices with the plurality of LED bond areas such that the first bond medium physically contacts the second bond medium; and
wafer bonding the first wafer to the second wafer by bonding the first bond medium to the second bond medium, in which the first bond medium and the second bond medium adjust for thickness variations in the first wafer and the second wafer to reduce voids in said bond medium.

2. The method of claim 1 , wherein the first wafer is a device wafer comprising at least one substrate.

3. The method of claim 2 , wherein the first wafer further comprises an epitaxial layer on the at least one substrate.

4. The method of claim 1 , wherein the second wafer is a submount wafer.

5. The method of claim 1 , wherein the first bond medium and the second bond medium comprise thermally conducting material.

6. The method of claim 1 , wherein the total thickness of the bond medium is 50-100 microns.

7. The method of claim 1 , wherein the first bond medium is further deposited on the second surface.

8. The method of claim 1 , wherein the at least one metal is selected from the group consisting of In, Pdln, PbSn, AgSn, AuSi, AuSn, and mixtures thereof.

9. The method of claim 1 , wherein at least one of the first wafer and the second wafer comprises a material selected from the group consisting of sapphire, GaAs, GaP, AlN, GaN, Si, SiC, and mixtures thereof.

10. A method of fabricating an electronic device using wafer level bonding, comprising:
providing a first wafer having a first surface, the first wafer comprising a first material, at least one substrate, and a plurality of said electronic devices, in which the plurality of the electronic devices are accessible from the first surface, the first wafer having a first coefficient of thermal expansion (CTE) and a total thickness variation (TTV) of 1 to 7 microns;
providing a second wafer having a second surface, said second surface comprising a second material dissimilar from said first material and a plurality of device bond areas, the second wafer having a second CTE with a thermal mismatch from said first CTE and a TTV of 1 to 7 microns;
forming a first bond medium preform on said first surface of said first wafer and a second bond medium preform on said second surface of said second wafer, said first and second bond medium preforms comprising an electrically conducting material such as at least one metal, a total thickness of the first and second bond medium preforms being approximately 10 microns or greater, the thickness of the first bond medium preform differing from the thickness of the second bond medium preform by at least one micron;
positioning the first wafer on said second wafer such that said first bond medium preform physically contacts said second bond medium preform; and
thinning the at least one substrate of the first wafer to a thickness of about the total thickness of the first and second bond medium preforms;
wherein the first and second bond medium preforms reduce effects of said CTE mismatch and adjust for thickness variations in the first wafer and the second wafer during wafer bonding.

11. The method of claim 10 , wherein the total thickness of the first and second bond medium preforms is about 20 microns or less.

12. The method of claim 10 , wherein the total thickness of the first and second bond medium preforms is 50-100 microns.

13. The method of claim 12 , wherein the first wafer further comprises an epitaxial layer on the at least one substrate.

14. The method of claim 10 , wherein the second wafer comprises a submount wafer.

15. The method of claim 2 , further comprising removing the at least one substrate from the device wafer, wherein the at least one substrate is removed after wafer bonding.

Assignees

• Chitnis Ashay
• Cree Inc

Inventors

• Chitnis Ashay

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10H20/8312

  extending at least partially through the bodies · CPC title

• H10H20/858

  Means for heat extraction or cooling · CPC title

• H10H20/018 Primary

  Bonding of wafers · CPC title

• H01L33/64

  Electricity · mapped topic