Display substrate, method of manufacturing display substrate, and display device including display substrate

Patent metadata

Field	Value
Publication number	US-10872944-B2
Application number	US-201916681697-A
Country	US
Kind code	B2
Filing date	Nov 12, 2019
Priority date	Nov 26, 2018
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.

First claim

What is claimed is:

1. A method of manufacturing a display substrate, the method comprising:
forming a semiconductor member that overlaps a pixel area of a substrate;
forming a gate electrode that overlaps the semiconductor member;
forming a source electrode and a drain electrode that directly contact the semiconductor member;
forming a pad electrode that overlaps a pad area of the substrate;
forming an inorganic insulation layer that covers each of the source electrode, the drain electrode, and the pad electrode;
forming an organic insulation member on the inorganic insulation layer, wherein the organic insulation member has a first positive maximum thickness in a direction perpendicular to the substrate at the pixel area of the substrate, has a second positive maximum thickness in the direction perpendicular to the substrate less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode;
removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer using an etching gas; and
partially removing the organic insulation member to form a planarization layer.

2. The method of claim 1 , wherein the source electrode, the drain electrode, and the pad electrode are simultaneously formed.

3. The method of claim 1 , wherein the pad electrode includes an intermediate layer including aluminum (Al) and includes two conductive layers respectively disposed on two opposite surfaces of the intermediate layer.

4. The method of claim 1 , wherein the inorganic insulation layer is formed of silicon nitride.

5. The method of claim 1 , wherein the organic insulation member is formed using a halftone mask.

6. The method of claim 5 , wherein forming the organic insulation member includes:
forming an organic insulation layer on the inorganic insulation layer;
exposing the organic insulation layer to a light using the halftone mask; and
partially removing the organic insulation layer.

7. The method of claim 6 , comprising:
positioning a first light transmitting portion of the halftone mask and a second light transmitting portion of the halftone mask over the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer, respectively;
positioning a light shielding portion of the halftone mask over the pixel area of the substrate, wherein the light shielding portion of the halftone mask exposes the first portion of the inorganic insulation layer; and
positioning a light transflective portion of the halftone mask over the pad area of the substrate, wherein the light transflective portion of the halftone mask exposes the second portion of the inorganic insulation layer.

8. The method of claim 1 , wherein the second portion of the inorganic insulation layer is disposed on a portion of an upper surface of the pad electrode before being removed.

9. The method of claim 1 , wherein the etching gas includes fluorine (F).

10. The method of claim 1 , wherein the organic insulation member is ashed by a thickness greater than or equal to the second positive maximum thickness and less than the first positive maximum thickness to form the planarization layer.

11. The method of claim 1 , wherein the organic insulation member is ashed by a thickness less than the second positive maximum thickness to form the planarization layer.

12. The method of claim 1 , further comprising:
forming a pixel electrode layer on the planarization layer, the pixel electrode layer being in contact with the drain electrode and the pad electrode; and
removing a portion of the pixel electrode layer that overlaps the pad area of the substrate.

13. The method of claim 12 , wherein the pixel electrode layer includes an intermediate layer including silver (Ag) and includes two conductive layers respectively disposed on two opposite surfaces of the intermediate layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Sang Gab
• Cho Hyunmin
• Kim Taesung
• Bae Subin
• Jeong Yu-Gwang
• Kim Jinseock

Classifications

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title