Solid-state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-10872919-B2
Application number	US-201716069448-A
Country	US
Kind code	B2
Filing date	Jan 13, 2017
Priority date	Jan 29, 2016
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

Provided are a solid-state imaging device and an electronic apparatus that include a charge storage unit. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to the hole.

First claim

The invention claimed is:

1. A solid-state imaging device, comprising:
a pixel array including a plurality of unit pixels; and
a circuit configured to control an operation of the plurality of unit pixels,
wherein each of the plurality of unit pixels includes:
a photodiode configured to generate a charge;
a trench capacitor configured to store the charge generated by the photodiode; and
a reverse-side deep trench isolation (RDTI) joined to the trench capacitor,
wherein the RDTI is adjacent to the trench capacitor.

2. The solid-state imaging device according to claim 1 , wherein
the trench capacitor is between the photodiode of a first unit pixel of the plurality of unit pixels and the photodiode of a second unit pixel of the plurality of unit pixels, and
the first unit pixel is adjacent to the second unit pixel.

3. The solid-state imaging device according to claim 1 , wherein
each of the plurality of unit pixels further includes a plurality of photodiodes,
the trench capacitor is one of between the plurality of photodiodes or between a first photodiode of the plurality of photodiodes of a first unit pixel of the plurality of unit pixels and a second photodiode of the plurality of photodiodes of a second unit pixel of the plurality of unit pixels, and
the first unit pixel is adjacent to the second unit pixel.

4. The solid-state imaging device according to claim 1 , wherein the trench capacitor penetrates a substrate.

5. The solid-state imaging device according to claim 1 , wherein
a potential of one end of the trench capacitor is one of a ground potential, a power-supply potential, or a specific potential.

6. The solid-state imaging device according to claim 5 , wherein
the potential of the one end of the trench capacitor is set at a first potential at a storing time of the photodiode,
the potential of the one end of the trench capacitor is set at a second potential at a reading time of the photodiode, and
the first potential is different from the second potential.

7. The solid-state imaging device according to claim 1 , wherein the solid-state imaging device is of a backside-illuminated type.

8. An electronic apparatus, comprising:
a solid-state imaging device including:
a pixel array including a plurality of unit pixels; and
a circuit configured to control an operation of the plurality of unit pixels, wherein
each of the plurality of unit pixels includes:
a photodiode configured to generate a charge;
a trench capacitor configured to store the charge generated by the photodiode; and
a reverse-side deep trench isolation (RDTI) joined to the trench capacitor,
 wherein the RDTI is adjacent to the trench capacitor;

a signal processing circuit configured to process an output signal output from the solid-state imaging device; and
an optical system configured to provide incident light to the solid-state imaging device.

Assignees

• Sony Corp

Inventors

• Takizawa Masaaki
• Tateshita Yasushi
• Toyoshima Takahiro
• TOYOFUKU Takuya
• Sakano Yorito
• Torii Motonobu

Classifications

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H04N25/53

  Control of the integration time · CPC title

• H04N25/585

  with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title