Semiconductor Power Module Comprising Graphene
US-2019333838-A1 · Oct 31, 2019 · US
US10872830B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10872830-B2 |
| Application number | US-201916529295-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 1, 2019 |
| Priority date | Feb 1, 2017 |
| Publication date | Dec 22, 2020 |
| Grant date | Dec 22, 2020 |
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A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.
Opening claim text (preview).
The invention claimed is: 1. A power semiconductor module, comprising: a base plate; a Si chip comprising a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against a side of the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; a second metal preform pressed with a second press pin against a side of the wide bandgap material chip; wherein the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; wherein the first metal preform is adapted for forming a conducting path through the Si chip by forming an alloy with the Si substrate, when heated by an overcurrent; wherein the second metal preform, which is made of a material with a higher melting point as a material of the first metal preform, is adapted for forming an at least temporary conducting path through the wide bandgap material chip, when heated by an overcurrent. 2. The power semiconductor module of claim 1 , wherein the second metal preform is adapted for forming an at least temporary conducting path through the wide bandgap material chip by at least partially being melted by the overcurrent. 3. The power semiconductor module of claim 1 , wherein the first metal preform is made of Al, Cu, Ag, Mg or an alloy thereof. 4. The power semiconductor module of claim 1 , wherein the second metal preform is made of Mo, W or an alloy thereof. 5. The power semiconductor module of claim 1 , wherein the base plate is made of Mo. 6. The power semiconductor module of claim 1 , wherein the wide bandgap material of the wide bandgap material chip is SiC. 7. The power semiconductor module of claim 1 , wherein the Si chip comprises a semiconductor switch provided in the Si substrate. 8. The power semiconductor module of claim 7 , wherein a gate of the semiconductor switch of the Si chip is electrically connected in the semiconductor module with a gate of the semiconductor switch of the wide bandgap material chip. 9. The power semiconductor module of claim 7 , wherein a gate of the semiconductor switch of the Si chip is electrically connected to a first gate terminal of the semiconductor module and a gate of the semiconductor switch of the wide bandgap material chip is electrically connected to a second gate terminal of the semiconductor module, such that the semiconductor switch of the Si chip is switchable independently of the semiconductor switch of the wide bandgap material chip. 10. The power semiconductor module of claim 7 , wherein a gate of the semiconductor switch of the Si chip is not connected to a gate terminal provided by the semiconductor module. 11. The power semiconductor module of claim 1 , wherein the Si chip does not comprise an active switchable switch. 12. The power semiconductor module of claim 1 , wherein the Si chip is a passive Si layer. 13. The power semiconductor module of claim 1 , wherein the power semiconductor module comprises at least two wide bandgap material chips connected in parallel with the Si chip. 14. The power semiconductor module of claim 1 , further comprising: an electrically conducting top plate connected to the first press pin and the second press pin. 15. The power semiconductor module of claim 1 , wherein at least one of the first press pin and the second press pin comprises a spring element. 16. The power semiconductor module of claim 2 , wherein the first metal preform is made of Al, Cu, Ag, Mg or an alloy thereof. 17. The power semiconductor module of claim 1 , wherein the second metal preform is made of Mo, W or an alloy thereof; and wherein the base plate is made of Mo. 18. The power semiconductor module of claim 2 , wherein the wide bandgap material of the wide bandgap material chip is SiC. 19. The power semiconductor module of claim 2 , wherein the Si chip comprises a semiconductor switch provided in the Si substrate. 20. The power semiconductor module of claim 17 , wherein the wide bandgap material of the wide bandgap material chip is SiC.
On the same surface · CPC title
Interconnections or connectors in packages · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
changes in dispositions · CPC title
Package configurations · CPC title
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