Memory modules, memory systems, and methods of operating memory modules

Patent metadata

Field	Value
Publication number	US-10872653-B2
Application number	US-201916390460-A
Country	US
Kind code	B2
Filing date	Apr 22, 2019
Priority date	Oct 17, 2018
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. The control device receives a command, an address, and a clock signal from an external device, and provides the command, the address, and the clock signal to the semiconductor memory devices. The control device, in a hidden training mode during a normal operation, performs a command/address training on at least one semiconductor memory device of the semiconductor memory devices by transmitting a first command/address and a first clock signal to the at least one semiconductor memory device and receiving a second command/address and a second clock signal in response to the first command/address and the first clock signal, from the at least one semiconductor memory device.

First claim

What is claimed is:

1. A memory module comprising:
a plurality of semiconductor memory devices mounted on a circuit board, at least one semiconductor memory device of the plurality of semiconductor memory devices including a loopback circuit, the loopback circuit including a first selection circuit and a second selection circuit; and
a control device mounted on the circuit board, and configured to receive a command, an address, and a clock signal from an external device and to provide the command, the address, and the clock signal to the plurality of semiconductor memory devices,
wherein the control device, in a hidden training mode during a normal operation, is configured to perform a command/address training on the at least one semiconductor memory device by transmitting a first command/address and a first clock signal to the at least one semiconductor memory device, and receiving a second command/address and a second clock signal in response to the first command/address and the first clock signal, from the at least one semiconductor memory device,
wherein the first selection circuit is configured to select one of the first command/address or a data signal in response to a selection signal based on the hidden training mode, and the second selection circuit is configured to select one of the first clock signal or a data strobe signal in response to the selection signal.

2. The memory module of claim 1 , wherein the at least one semiconductor memory device is configured to transmit the second command/address and the second clock signal to the control device through a first loopback pin and a second loopback pin, respectively, in the hidden training mode, under control of the control device.

3. The memory module of claim 2 ,
wherein the loopback circuit further includes:
a first transmitter coupled to the first selection circuit and the first loopback pin; and
a second transmitter coupled to the second selection circuit and the second loopback pin.

4. The memory module of claim 3 , wherein in the hidden training mode,
the first selection circuit is configured to select the first command/address in response to the selection signal to provide the first command/address to the first transmitter, and
the second selection circuit is configured to select the first clock signal in response to the selection signal to provide the first clock signal to the second transmitter.

5. The memory module of claim 3 , wherein
the first selection circuit includes a first switch that has a first terminal configured to receive the first command/address, a second terminal configured to receive the data signal, and a third terminal coupled to the first transmitter, and
the second selection circuit includes a second switch that has a first terminal configured to receive the first clock signal, a second terminal configured to receive the data strobe signal, and a third terminal coupled to the second transmitter.

6. The memory module of claim 3 , wherein
the first selection circuit includes a first multiplexer that has a first input terminal configured to receive the first command/address, a second input terminal configured to receive the data signal, an output terminal coupled to the first transmitter, and a control terminal configured to receive the selection signal, and
the second selection circuit includes a second multiplexer that has a first input terminal configured to receive the first clock signal, a second input terminal configured to receive the data strobe signal, an output terminal coupled to the second transmitter, and a control terminal configured to receive the selection signal.

7. The memory module of claim 1 , wherein the control device includes an interface circuit,
wherein the interface circuit is configured to perform the command/address training in the hidden training mode by:
receiving the second command/address and the second clock signal;
detecting a skew between the second command/address and the second clock signal; and
adjusting a delay of the first command/address based on the detected skew, and
wherein the interface circuit is configured to detect the skew by detecting a difference between an edge of the second clock signal and a center of the second command/address.

8. The memory module of claim 7 , wherein the interface circuit includes:
a delay-locked loop circuit configured to receive the second command/address and the second clock signal, to detect the skew between the second command/address and the second clock signal, and to output a skew information on the detected skew, in the hidden training mode; and
a delay circuit configured to adjust an amount of the delay of the first command/address based on the skew information to output an adjusted command/address.

9. The memory module of claim 8 , wherein the control device is configured to receive the second command/address and the second clock signal from the at least one semiconductor memory device through a first loopback pin and a second loopback pin, respectively, in the hidden training mode.

10. The memory module of claim 8 , wherein the interface circuit is configured to perform an initial command/address training on the at least one semiconductor memory device to obtain an initial skew information based on the initial command/address training,
the interface circuit further includes a register configured to store the initial skew information, and
the delay circuit is configured to adjust an amount of the delay of the first command/address based on a comparison of the initial skew information and the skew information.

11. The memory module of claim 1 , wherein the control device includes an interface circuit, and
wherein the interface circuit is configured to perform the command/address training in the hidden training mode by:
receiving the second command/address and the second clock signal;
detecting a phase difference between an edge of the first clock signal and an edge of the second clock signal; and
adjusting a delay of the first command/address based on the detected phase difference.

12. The memory module of claim 11 , wherein the interface circuit includes:
a delay-locked loop circuit configured to receive the second command/address and the second clock signal, to detect the phase difference between the edge of the first clock signal and the edge of the second clock signal, and to output a skew information on the detected phase difference, in the hidden training mode; and
a delay circuit configured to adjust an amount of the delay of the first command/address based on the skew information to output an adjusted command/address.

13. The memory module of claim 1 , wherein the control device includes an interface circuit,
wherein the interface circuit is configured to perform the command/address training in the hidden training mode by:
receiving the second command/address and the second clock signal;
detecting a skew between the first command/address and the second command/address; and
adjusting a delay of the first command/address based on the detected skew, and
wherein the interface circuit is configured to detect the skew by detecting a difference between a center of the first command/address and a center of the second command/address.

14. The memory module of claim 13 , wherein the interface circuit includes:
a delay-locked loop circuit configured to receive the second command/address and the second clock signal, to detect the skew between the center of the first command/address and the center of the second command/address, and to output a skew information on the detected skew, in the hidden training mode; and
a delay cir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong-Hoon
• Yun Young
• Kim Wang-Soo
• Kwon Yoo-Jeong
• Ryu Si-Hoon
• Lee Young-Ho
• Park Sung-Joo

Classifications

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title