Integrated circuit for nonlinear data encoding

Patent metadata

Field	Value
Publication number	US-10872553-B2
Application number	US-201916396366-A
Country	US
Kind code	B2
Filing date	Apr 26, 2019
Priority date	Oct 7, 2015
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A method of image processing, the method including performing linear processing of an input data signal encoded with a nonlinear function to generate a linear representation of the input data signal including linearized image data, and using an integrated circuit to generate a processed linear image by nonlinearly quantizing the linearized image data to generate nonlinear quantized data, generating a memory address based on the nonlinear quantized data, and accessing a lookup table based on the generated memory address.

First claim

What is claimed is:

1. A method of nonlinear encoding, the method comprising:
receiving a linearized data;
identifying a data block of a plurality of data blocks that contains the linearized data, wherein each data block corresponds to a boundary slice, an offset, and a block bit shift;
bit-shifting the linearized data according to the block bit shift of the data block to generate most significant bits;
bit shifting the boundary slice of a previous data block according to the block bit shift to generate a boundary slice offset; and
generating a nonlinear quantized data according to the most significant bits, the offset, and the boundary slice offset.

2. The method of claim 1 , further comprising:
receiving an image data encoded with a nonlinear function; and
performing linear processing on the image data to generate the linearized data.

3. The method of claim 2 , further comprising performing image processing on the linearized data.

4. The method of claim 3 , wherein the image processing comprises adjusting at least one of a color, contrast, and brightness of the linearized data.

5. The method of claim 1 , wherein generating the nonlinear quantized data comprises summing the most significant bits with the offset, and subtracting the boundary slice offset.

6. The method of claim 1 , further comprising generating a memory address based on the nonlinear quantized data; and retrieving an output value from a lookup table that is located at the memory address.

7. The method of claim 6 , further comprising:
calculating an error of the output value; and
modifying at least one of the boundary slice, offset, and block bit shift when the error of the output value exceeds an error tolerance.

8. A compressive lookup table implemented by:
at least one register for storing a boundary slice, a block bit shift, and an offset for each data block of a plurality of data blocks;
a compressive addressing computation processor configured to receive a linearized input data and to perform a quantization function on the linearized input data,
wherein performing a quantization function on the linearized input data comprises:
identifying a data block from the plurality of data blocks that contains the linearized input data;
bit-shifting the linearized input data according to a block bit shift of the data block to generate most significant bits;
bit-shifting the boundary slice of a previous data block according to the block bit shift to generate a boundary slice offset; and
generating a nonlinear quantized data according to the most significant bits, the offset, and the boundary slice offset.

9. The compressive lookup table of claim 8 , wherein generating the nonlinear quantized data comprises summing the most significant bits with the offset, and subtracting the boundary slice offset.

10. The compressive lookup table of claim 8 comprising a lookup table for storing a plurality of output values at a plurality of memory addresses, the compressive lookup table further being implemented by a memory controller configured to access plurality of memory addresses of the lookup table to retrieve an output value.

11. The compressive lookup table of claim 10 , wherein performing a quantization function on the linearized input data further comprises generating a memory address based on the nonlinear quantized data.

12. The compressive lookup table of claim 11 , wherein the memory controller is configured to retrieve the output value from the lookup table using the memory address.

13. The compressive lookup table of claim 12 , wherein the lookup table is configured to:
calculate an error of the output value; and
modify at least one of the boundary slice, offset, and block bit shift for the data block when the error of the output value exceeds an error tolerance.

14. The compressive lookup table of claim 11 , wherein the compressive lookup table is further implemented by an integrated circuit.

15. The compressive lookup table of claim 14 , wherein the integrated circuit comprises a single memory cell corresponding to the lookup table.

16. The compressive lookup table of claim 15 , wherein the single memory cell is reprogrammable.

17. The compressive lookup table of claim 8 , wherein the at least one register comprises:
a boundary slice register for determining a boundary of the data block of the linearized input data corresponding to the linearized input data;
a block bit shift register for determining a block bit shift corresponding to the data block; and
an offset register for determining an offset corresponding to the data block.

18. A method of image processing comprising:
receiving an input image data encoded with a nonlinear function;
generating a linearized image data by performing linear processing on the input image data; and
retrieving an output value associated with the linearized image data,
wherein the retrieving the output value comprises:
determining a data block of a plurality of data blocks that contains the linearized image data wherein each data block of the plurality of data block corresponds to a boundary slice, a block bit shift, and an offset;
dividing the linearized image data according to the block bit shift corresponding to the data block to generate most significant bits;
dividing the boundary slice of an adjacent data block by the block bit shift to generate a boundary slice offset;
calculating a memory address by subtracting boundary slice offset from the most significant bits and adding an offset of the data block; and
retrieving the output value from the memory address.

19. The method of claim 18 , further comprising performing image processing on the linearized image data by adjusting at least one of a color, contrast, and brightness of the linearized image data.

20. The method of claim 18 , further comprising:
calculating an error of the output value; and
modifying at least one of the boundary slice, offset, and block bit shift when the error of the output value exceeds an error tolerance.

Assignees

• Samsung Display Co Ltd

Inventors

• Hoffman David M

Classifications

• H04N19/126 Primary

  Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers · CPC title

• H04N19/124

  Quantisation · CPC title

• H04N19/117

  Filters, e.g. for pre-processing or post-processing (sub-band filter banks H04N19/635) · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G09G2320/0276

  for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction · CPC title