Methods and apparatus for an analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10868563-B2
Application number	US-201916455114-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Mar 13, 2019
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Various embodiments of the present technology may comprise methods and apparatus for an analog-to-digital converter. Methods and apparatus for an analog-to-digital converter (ADC) may be configured as a delta-sigma type ADC and include an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier. The switched-capacitor circuits receive various control signals such that one SC circuit performs sampling while the other SC circuit simultaneously performs integration.

First claim

The invention claimed is:

1. A delta-sigma analog-to-digital converter, comprising:
a first integrator circuit, comprising:
a first switched-capacitor circuit configured to receive a first input signal and a second input signal and comprising: a first sampling capacitor and a second sampling capacitor;
a second switched-capacitor circuit configured to receive the first input signal and the second input signal and comprising: a third sampling capacitor and a fourth sampling capacitor;
a first amplifier comprising a first non-inverting input terminal and a first inverting input terminal, wherein:
the first switched-capacitor circuit is connected to the first non-inverting input terminal and the first inverting input terminal; and
the second switched-capacitor circuit is connected to the first non-inverting input terminal and the first inverting input terminal;

a first pair of digital-to-analog converters selectively connected to the first and second sampling capacitors; and
a second pair of digital-to-analog converters selectively connected to the third and fourth sampling capacitors.

2. The delta-sigma analog-to-digital converter according to claim 1 , further comprising a second integrator circuit connected in series with the first integrator circuit, wherein the second integrator circuit comprises:
a third switched-capacitor circuit;
a fourth switched-capacitor circuit; and
a second amplifier comprising a second non-inverting input terminal and a second inverting input terminal, wherein:
the third switched-capacitor circuit is connected to the second non-inverting input terminal and the second inverting input terminal; and
the fourth switched-capacitor circuit is connected to the second non-inverting input terminal and the second inverting input terminal.

3. The delta-sigma analog-to-digital converter according to claim 2 , wherein the second integrator circuit further comprises: a plurality digital-to-analog converters responsive to a control signal and directly connected to at least one of the third and fourth switched-capacitor circuits.

4. The delta-sigma analog-to-digital converter according to claim 2 , further comprising a quantizer connected directly to an output terminal of the second amplifier and configured to generate a digital output value.

5. The delta-sigma analog-to-digital converter according to claim 4 , wherein:
the delta-sigma analog-to-digital converter operates according to a reference clock signal having a first frequency;
the quantizer operates according to a quantizer clock signal having the first frequency; and
the first and second switched-capacitor circuits operate according to a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal are non-overlapping signals having a second frequency that is half that of the first frequency.

6. The delta-sigma analog-to-digital converter according to claim 4 , further comprising a plurality digital-to-analog converters responsive to the digital output value of the quantizer and connected to at least one of the first and second switched-capacitor circuits.

7. The delta-sigma analog-to-digital converter according to claim 1 , further comprising a plurality of digital-to-analog converters connected to at least one of the first and second switched-capacitor circuits via a switch.

8. The delta-sigma analog-to-digital converter according to claim 7 , wherein each digital-to-analog converter from the plurality of digital-to-analog converters is responsive to a control signal based on a quantizer output, a first digital signal based on a reference clock, and a second digital signal based on the reference clock.

9. A method for operating an analog-to-digital converter, comprising:
performing integration using a first switched-capacitor circuit, comprising a first sampling capacitor and a second sampling capacitor, and according to a first clock signal;
performing sampling using a second switched-capacitor circuit, comprising a third sampling capacitor and a fourth sampling capacitor, and according to a second clock signal;
wherein:
the first clock signal and the second clock signal are non-overlapping signals having a first frequency; and
integration and sampling are performed simultaneously.

10. The method according to claim 9 , wherein the analog-to-digital converter operates according to a reference clock having a second frequency.

11. The method according to claim 10 , further comprising performing quantization according to a quantizer clock having a third frequency that is the same as the second frequency.

12. The method according to claim 11 , wherein the first frequency is half of the third frequency.

13. A system, comprising:
a signal generator circuit configured to generate:
a first clock signal and a second clock signal according to a reference clock signal having a first frequency, wherein the first and second clock signals are non-overlapping signals having a second frequency that is half that of the first frequency; and
a quantizer clock signal according to the reference clock signal, wherein the quantizer clock signal has the first frequency; and

an analog-to-digital converter in communication with the signal generator circuit, and comprising:
a first integrator circuit comprising four sampling capacitors and configured to simultaneously perform integration and sampling according to the first clock signal and the second clock signal;
a second integrator circuit connected in series with the first integrator circuit and configured to simultaneously perform integration and sampling according to the first clock signal and the second clock signal; and
a quantizer connected to an output of the second integrator circuit and configured to:
perform quantization according to the quantizer clock signal having the first frequency; and
generate a digital output.

14. The system according to claim 13 , wherein the first integrator circuit comprises:
a first switched-capacitor circuit configured to receive a first input signal and a second input signal;
a second switched-capacitor circuit configured to receive the first input signal and the second input signal; and
a first amplifier comprising a first non-inverting input terminal and a first inverting input terminal, wherein:
the first switched-capacitor circuit is connected to the first non-inverting input terminal and the first inverting input terminal; and
the second switched-capacitor circuit is connected to the first non-inverting input terminal and the first inverting input terminal.

15. The system according to claim 14 , further comprising a plurality of digital-to-analog converters connected to at least one of the first and second switched-capacitor circuits via a switch, wherein each digital-to-analog converter from the plurality of digital-to-analog converters is responsive to:
a control signal based on the digital output of the quantizer,
a first digital signal based on the reference clock signal, and
a second digital signal based on the reference clock signal.

16. The system according to claim 13 , wherein the second integrator circuit comprises:
a third switched-capacitor circuit;
a fourth switched-capacitor circuit; and
a second amplifier comprising a second non-inverting input terminal and a second inverting input terminal, wherein:
the third switched-capacitor circuit is connected to the second non-inverting input terminal and the second inverting input terminal; and
the fourth switched-capacitor circuit is connected to the second non-inverting input terminal an

Assignees

• Semiconductor Components Ind Llc

Inventors

• Onishi Akinobu

Classifications

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/392 Primary

  Arrangements for selecting among plural operation modes, e.g. for multi-standard operation · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/412

  characterised by the number of quantisers and their type and resolution · CPC title