Low distortion successive approximation register (SAR) analog-to-digital converters (ADCs) and associated methods

Patent metadata

Field	Value
Publication number	US-10868560-B2
Application number	US-201916708701-A
Country	US
Kind code	B2
Filing date	Dec 10, 2019
Priority date	Sep 28, 2017
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage V ref =M*V DD , where M<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where V ref =M*V DD , where M<1, wherein the first capacitor having a capacitive value that is equal to (1−M)times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (V IN ) signal as the second input to the comparator.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) device comprising:
a successive approximation register (SAR) configured to generate a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage;
a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal,
wherein the DAC includes:
a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio M is equal to the reference voltage divided by the first voltage;
one or more first capacitors; and
a plurality of second capacitors coupled to the reference voltage,

wherein the redistribution capacitor's capacitance is equal to (1−M) times a total capacitance of a parallel combination of the one or more first capacitors,
wherein the plurality of second capacitors are associated with the plurality of less significant bits.

2. The ADC of claim 1 , wherein:
the SAR is configured to perform a binary search to test each possible bit of the parallel digital output,
wherein beginning with the MSB each bit is tested by comparing, by a comparator, the internal analog signal to an input voltage V IN , and
based upon the comparator sensing that the internal analog signal exceeds the input voltage V IN , the comparator asserts a signal causing the SAR to either de-assert the tested bit or to set the tested bit.

3. The ADC of claim 2 , wherein the input voltage V IN is sampled from a varying analog signal by a sample and hold circuit.

4. The ADC of claim 1 , wherein based upon the MSB remaining high during testing, one or more of the first capacitors associated with one or more more-significant bits is tied to a supply voltage V DD .

5. The ADC of claim 1 , wherein the SAR implements a successive approximation algorithm.

6. The ADC of claim 1 , wherein the one or more first capacitors is associated with one or more less significant bits in addition to the MSB.

7. The ADC of claim 1 , wherein at the SAR performs a binary search of values of the parallel digital output.

8. The ADC of claim 1 , further comprising a plurality of switches respectively configured to decouple the plurality of second capacitors from the reference voltage.

9. A method for performing an analog-to-digital conversion, the method comprising:
supplying an output of a comparator to an input of a successive approximation register (SAR) to generate based thereon a parallel digital output having a most significant bit (MSB), and a plurality of less significant bits;
supplying the parallel digital output to a digital-to-analog converter (DAC) to generate based thereon an internal analog signal,
wherein the DAC includes a first capacitor, a plurality of second capacitors, and a plurality of third capacitors,
wherein the first capacitor is coupled between a first line carrying a first voltage and a second line carrying a second voltage,
wherein the plurality of second capacitors is each switchable coupled between the first line and the second line and having respectively a value less than the first voltage,
wherein the plurality of third capacitors is associated with the less significant bits and respectively switchably coupled between the first line and a third line carrying the third voltage.

10. The method of claim 9 , wherein:
the SAR performs a binary search to test each possible bit of the parallel digital output,
wherein beginning with the MSB each bit is tested by comparing, by the comparator, the internal analog signal to an input voltage (V IN ) to the comparator; and
based upon the comparator sensing that the internal analog signal exceeds V IN , the comparator asserts a signal causing the SAR to either de-assert the tested bit or set the tested bit.

11. The method of claim 9 , wherein the internal analog signal is generated by voltage division across a plurality of capacitors.

12. The method of claim 9 , wherein the first voltage is V DD .

13. The method of claim 12 , wherein the first voltage is V SS .

14. The method of claim 13 , wherein the third voltage is a reference voltage V REF .

15. The method of claim 9 , wherein based upon the MSB being set high and the less significant bits being set low, the internal analog signal is equal to V REF /2.

16. The method of claim 9 , further comprising providing a plurality of switches respectively configured to switchably couple the first capacitor to the first line and to switchably couple the plurality of third capacitors from the third voltage line.

17. A digital-to-analog converter (DAC), comprising:
a first capacitor and a plurality of second capacitors, the first capacitor being coupled to a first line and a second line, and the plurality of second capacitors being coupled to the second line and to a first node switchably coupled by a first switch to a third line carrying a reference voltage, and
wherein the first capacitor is not connected or switchably adapted to connect to the third line,
wherein the first line carries a first voltage greater than the reference voltage, and
wherein a successive approximation register (SAR) controls the first switch.

18. The DAC of claim 17 , wherein the first voltage is a supply voltage V OO .

19. The DAC of claim 17 , further comprising a plurality of switches respectively configured to switchably couple the first capacitor to the first voltage when one or more capacitors associated with more significant bits are also switchably coupled to the first voltage, wherein the plurality of switches are controlled by signals from the SAR.

20. The DAC of claim 17 , wherein the SAR performs a successive approximation algorithm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Mei-Chen

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M1/0614

  of harmonic distortion (H03M1/0617 takes precedence) · CPC title

• H03M1/46 Primary

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/802

  using capacitors, e.g. neuron-mos transistors, charge coupled devices · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title