Co-fired passive integrated circuit devices

US10868243B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10868243-B2
Application numberUS-201916586787-A
CountryUS
Kind codeB2
Filing dateSep 27, 2019
Priority dateMar 31, 2015
Publication dateDec 15, 2020
Grant dateDec 15, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Co-fired integrated circuit devices and methods for fabricating and integrating such on a workpiece are disclosed herein. An exemplary method includes forming a first passive device and a second passive device over a carrier substrate. The first passive device and the second passive device each include at least one material layer that includes a co-fired ceramic material. The carrier substrate is removed after performing a co-firing process to cause chemical changes in the co-fired ceramic material. The first passive device may include a conductive loop disposed between a first magnetic layer and a second magnetic layer. The first magnetic layer, the second magnetic layer, or both includes a co-fired ceramic magnetic material. The second passive device may include a first conductive layer and a second conductive layer separated by a dielectric layer. The first conductive layer, the second conductive layer, or both includes a co-fired ceramic conductive material.

First claim

Opening claim text (preview).

What is claimed is: 1. A device comprising: a first wafer including a first passive device, a first plurality of contacts of the first passive device, a second passive device, and a second plurality of contacts of the second passive device, wherein the first passive device is different than the second passive device, the first passive device is disposed laterally adjacent to the second passive device, and the first passive device and the second passive device each include at least one layer that includes a co-fired ceramic material; and a second wafer attached to the first wafer, wherein a circuit element of the second wafer is connected to the first passive device and the second passive device. 2. The device of claim 1 , wherein: the first passive device includes a conductive loop disposed between a first magnetic layer and a second magnetic layer, wherein the first magnetic layer, the second magnetic layer, or both includes a co-fired ceramic magnetic material; and the second passive device includes a first conductive layer and a second conductive layer separated by a dielectric layer, wherein the first conductive layer, the second conductive layer, or both includes a co-fired ceramic conductive material. 3. The device of claim 2 , wherein the first magnetic layer and the second magnetic layer both include the co-fired ceramic magnetic material. 4. The device of claim 2 , wherein the first conductive layer and the second conductive layer both include the co-fired ceramic conductive material. 5. The device of claim 2 , wherein the conductive loop includes a co-fired conductive material. 6. The device of claim 2 , wherein the dielectric layer includes a co-fired dielectric material. 7. The device of claim 2 , wherein the dielectric layer is a first dielectric layer and the first passive device further includes a second dielectric layer disposed between the conductive loop and the second magnetic layer. 8. The device of claim 1 , further comprising: a bonding structure that facilitates electrical coupling of the circuit element with the first passive device and the second passive device; and a dummy bonding structure that facilitates physical coupling without electrical coupling of the first passive device, the second passive device, or both with the second wafer. 9. The device of claim 8 , wherein: the bonding structure includes a first bonding structure that electrically couples the circuit element to the first passive device and a second bonding structure that electrically couples the circuit element to the second passive device; and the dummy bonding structure is disposed between the first bonding structure and the second bonding structure. 10. A device comprising: a circuit substrate that includes a voltage converter; and a passive device substrate bonded to the circuit substrate, wherein the passive device substrate includes: a dielectric layer, a capacitor disposed on the dielectric layer, wherein a bottommost surface of the capacitor directly contacts a top surface of the dielectric layer, wherein a first bonding structure electrically connects the capacitor to the voltage converter, an inductor disposed on the dielectric layer, wherein a bottommost surface of the inductor directly contacts the top surface of the dielectric layer, wherein a second bonding structure electrically connects the inductor to the voltage converter, and wherein the capacitor and the inductor each include at least one layer that includes a co-fired ceramic material. 11. The device of claim 10 , wherein a dummy bonding structure physically connects the inductor to the circuit substrate. 12. The device of claim 11 , wherein: the first bonding structure, the second bonding structure, and the dummy bonding structure each include a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. 13. The device of claim 12 , wherein the first conductive layer is formed of a first conductive material and the second conductive layer is formed of a second conductive material different in composition from the first conductive material. 14. The device of claim 12 , wherein the third conductive layer includes a co-fired ceramic material. 15. The device of claim 12 , wherein the third conductive layer of the first bonding structure defines a top plate of the capacitor. 16. The device of claim 12 , wherein the third conductive layer of the second bonding structure is disposed on a conductive loop of the inductor and the third conductive layer of the dummy bonding structure is disposed on the inductor. 17. The device of claim 10 , wherein the circuit substrate further includes an input/output transceiver. 18. A device comprising: a circuit element disposed on a substrate; a first co-fired ceramic passive device connected to the circuit element; a second co-fired ceramic passive device connected to the circuit element, wherein the second co-fired ceramic passive device is disposed laterally adjacent to the first co-fired ceramic passive device; a bonding structure that facilitates physical coupling and electrical coupling of the circuit element with the first co-fired ceramic passive device and the second co-fired ceramic passive device; and a dummy bonding structure that facilitates physical coupling without electrical coupling of the substrate with the first co-fired ceramic passive device. 19. The device of claim 18 , wherein the first co-fired ceramic passive device includes an inductor having a conductive loop extending through a ceramic magnetic material. 20. The device of claim 18 , wherein the second co-fired ceramic passive device includes a capacitor having a first conductive plate and a second conductive plate separated by a ceramic dielectric material.

Assignees

Inventors

Classifications

  • characterised by only passive components · CPC title

  • Electrodes · CPC title

  • Capacitors having no potential barriers · CPC title

  • Inductors · CPC title

  • H05K1/0306Primary

    Inorganic insulating substrates, e.g. ceramic, glass · CPC title

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What does patent US10868243B2 cover?
Co-fired integrated circuit devices and methods for fabricating and integrating such on a workpiece are disclosed herein. An exemplary method includes forming a first passive device and a second passive device over a carrier substrate. The first passive device and the second passive device each include at least one material layer that includes a co-fired ceramic material. The carrier substrate …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd, Apple
What technology area does this patent fall under?
Primary CPC classification H05K1/0306. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 15 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).