Manufacturing design and processing methods and apparatus for sputtering targets
US-9279178-B2 · Mar 8, 2016 · US
US10868212B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10868212-B2 |
| Application number | US-201314077548-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 12, 2013 |
| Priority date | Sep 10, 2009 |
| Publication date | Dec 15, 2020 |
| Grant date | Dec 15, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Epitaxial formation structures and associated methods of manufacturing solid state lighting (“SSL”) devices with target thermal expansion characteristics are disclosed herein. In one embodiment, an SSL device includes a composite structure having a composite CTE temperature dependency, a formation structure on the composite structure, and an SSL structure on the formation structure. The SSL structure has an SSL temperature dependency, and a difference between the composite CTE and SSL temperature dependencies is below 3 ppm/° C. over the temperature range.
Opening claim text (preview).
I claim: 1. An integrated semiconductor device assembly for use in forming a solid state lighting (SSL) device, the assembly comprising: a substrate comprising a composite ceramic material, the composite ceramic material having a composite coefficient of thermal expansion (CTE) temperature dependency over a temperature range from 800° C. to 1100° C.; a formation structure on the substrate, the formation structure comprising at least one of Si(1,1,1) silicon, gallium nitride (GaN), silicon carbide (SiC), sapphire (Al 2 O 3 ), zinc oxide (ZnO 2 ), or gallium arsenide (GaAs); and an SSL structure on the formation structure, the SSL structure having an SSL CTE temperature dependency over the temperature range, the SSL structure comprising a first semiconductor material including P-type gallium nitride, a second semiconductor material including N-type gallium nitride, and an active region, between the first and second semiconductor materials, comprising indium gallium nitride, wherein a difference between the composite CTE and SSL CTE temperature dependencies is below a target threshold of 0.3 ppm/° C. over the temperature range, and wherein the composite ceramic material comprises polycrystalline aluminum nitride (AlN), yttrium oxide (Y 2 O 3 ) and hafnium carbide (HfC) sintered together. 2. The assembly of claim 1 wherein the target threshold is below 0.1 ppm/° C. 3. The assembly of claim 1 wherein: the polycrystalline aluminum nitride comprises 0.4 to 0.7 by volume of the composite ceramic material, and the yttrium oxide comprises 0.01 to 0.2 by volume of the composite ceramic material.
Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title
with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title
the light-emitting regions comprising nitride materials · CPC title
having stress relaxation structures, e.g. buffer layers · CPC title
Bonding of wafers · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.