Systems and methods for forming nanowires using anodic oxidation

Patent metadata

Field	Value
Publication number	US-10868117-B2
Application number	US-201916715966-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Mar 31, 2014
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.

First claim

What is claimed is:

1. A structure comprising:
a semiconductor substrate;
a protruding structure on the semiconductor substrate; and
a nanostructure and a plurality of nano-vias in the protruding structure, the plurality of nano-vias comprising a first nano-via and a second nano-via, the first nano-via of the plurality of nano-vias being disposed closer to a major surface of the semiconductor substrate than the second nano-via of the plurality of nano-vias, wherein each nano-via of the plurality of nano-vias is filled with air.

2. The structure of claim 1 , wherein the semiconductor substrate includes a ridge section extending under the protruding structure.

3. The structure of claim 2 , wherein the nanostructure, each nano-via of the plurality of nano-vias, and the ridge section extend along a first direction.

4. The structure of claim 1 , wherein the nanostructure is a nanowire, a nanoslate, or a nanorod, wherein the nanostructure extends between a source region and a drain region of the structure.

5. The structure of claim 1 , wherein a ratio of a height of the protruding structure to a width of the protruding structure is greater than 1.

6. The structure of claim 1 , wherein the protruding structure comprises a dielectric material that surrounds the nanostructure and each nano-via of the plurality of nano-vias.

7. The structure of claim 6 , wherein a thickness of the dielectric material is greater in a lower portion of the protruding structure than in an upper portion of the protruding structure.

8. A device comprising:
a source region formed on a semiconductor substrate;
a drain region formed on the semiconductor substrate;
a protruding structure on the semiconductor substrate between the source region and the drain region; and
a nanostructure and a plurality of nano-vias between the source region and the drain region, wherein each nano-via of the plurality of nano-vias is between the nanostructure and the semiconductor substrate in a direction perpendicular to a major surface of the semiconductor substrate.

9. The device of claim 8 , wherein the semiconductor substrate includes a ridge section extending under the protruding structure.

10. The device of claim 9 , wherein:
each nano-via of the plurality of nano-vias extends along a first direction; and
the ridge section extends along the first direction.

11. The device of claim 8 , wherein the drain region is isolated from the semiconductor substrate.

12. The device of claim 8 , wherein the protruding structure includes a sidewall corresponding to a shape of which a top width is larger than a bottom width.

13. The device of claim 8 , wherein the protruding structure includes a dielectric material that surrounds each nano-via of the plurality of nano-vias.

14. The device of claim 13 , wherein a thickness of the dielectric material is greater in a lower portion of the protruding structure than in an upper portion of the protruding structure.

15. A structure comprising:
a semiconductor substrate;
one or more nano-vias over the semiconductor substrate;
a nanostructure over the one or more nano-vias; and
a protruding structure on the semiconductor substrate, the protruding structure comprising a dielectric material surrounding the nanostructure and each nano-via of the one or more nano-vias, a thickness of the dielectric material being greater in a lower portion of the protruding structure than in an upper portion of the protruding structure.

16. The structure of claim 15 , wherein:
the semiconductor substrate includes a ridge section that extends along the protruding structure;
each nano-via of the one or more nano-vias extends along a first direction; and
the ridge section extends along the first direction.

17. The structure of claim 15 , further comprising a source region and a drain region over the semiconductor substrate, wherein the nanostructure extends between the source region and the drain region, wherein the nanostructure is a nanowire, a nanoslate, or a nanorod.

18. The structure of claim 15 , wherein:
the protruding structure has a width and a height;
an aspect ratio of the protruding structure is equal to the height divided by the width; and
the aspect ratio is larger than 1.

19. The structure of claim 15 , wherein each nano-via of the one or more nano-vias is filled with air.

20. The structure of claim 1 , wherein sidewalls of the protruding structure narrow to a first local minimum, widen to a local maximum, and narrow to a second local minimum in a direction towards the semiconductor substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Hwu Jenn-Gwo
• Tian Wei-Cheng
• Tseng Po-Hao

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/6324

  Formation by anodic treatments, e.g. anodic oxidation · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/01

  Manufacture or treatment · CPC title