Device integrated with depletion-mode junction fielf-effect transistor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10867995-B2
Application number	US-201716329348-A
Country	US
Kind code	B2
Filing date	Aug 21, 2017
Priority date	Aug 31, 2016
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

First claim

What is claimed is:

1. A device integrated with a depletion-mode junction field-effect transistor, the device is divided into a Junction Field-Effect Transistor (JFET) region and a power device region, the device comprising:
a first conduction type drain, while a portion of the drain is configured to form the JFET region, and the other portion of the drain is configured to form the power device region; and
a first conduction type region located on a surface of the first conduction type drain facing a front face of the device, while a portion of the first conduction type region is configured to form the JFET region, and the other portion of the first conduction type region is configured to form the power device region; the JFET region comprising:
at least two second conduction type well regions formed within the first conduction type region, while the first conduction type is opposite to a second conduction type;
at least two JFET sources having a first conduction type, which are formed within the at least two second conduction type well regions respectively;
a metal electrode of a JFET source formed on the JFET source, which is in contact with the JFET source;
a lateral channel region being of the first conduction type, which is formed between two adjacent JFET sources, while two ends of the lateral channel region are in contact with the two adjacent JFET sources; and
a JFET metal gate formed on a second conduction type well region;
wherein the second conduction type well region comprises a first well and a second well located within the first well, while an ion concentration of the second well is greater than that of the first well;
the first well is located at a boundary between the JFET region and the power device region, to isolate the JFET region from the power device region.

2. The device according to claim 1 , wherein the JFET region further comprises at least two JFET gate ohmic contacts, while each of the JFET gate ohmic contacts is formed within each of second conduction type well regions where the two adjacent JFET sources are located, and is located on one side of the JFET source away from the lateral channel region, and has the second conduction type; the JFET metal gate is formed on the JFET gate ohmic contact and in contact with the JFET gate ohmic contact.

3. The device according to claim 1 , wherein the power device is a Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor (VDMOS).

4. The device according to claim 3 , wherein the power device region comprises:
a gate;
a second well;
a VDMOS first conduction type source located within the second well; and
a first unclamped inductive switching region located within the second well and under the VDMOS first conduction type source, which has the second conduction type and an ion concentration greater than that of the second well.

5. The device according to claim 4 , further comprising a second unclamped inductive switching region located under the JFET source and within the second well, which has the second conduction type and an ion concentration greater than that of the second well.

6. The device according to claim 4 , wherein two second wells are located at both sides under the gate respectively, the VDMOS first conduction type source is formed within the two second wells, and the VDMOS first conduction type source is divided into two blocks in each of the two second wells.

7. The device according to claim 6 , wherein further comprises a second conduction type ohmic contact region formed between the two blocks of the VDMOS first conduction type source.

8. The device according to claim 1 , wherein the first conduction type is an N type, the second conduction type is a P type, and the first conduction type region is an N type epitaxial layer.

9. A method for manufacturing a device integrated with a depletion-mode junction field-effect transistor, the device comprising a Junction Field-Effect Transistor (JFET) region and a power device region, the method comprising:
providing a substrate of a first conduction type on which a first conduction type region is formed; while the first conduction type is opposite to a second conduction type;
implanting ions of a second conduction type into the first conduction type region and forming a plurality of first wells within the first conduction type region by driving-in;
growing a field oxide layer and a gate oxide layer on a surface of the first conduction type region in sequence, and forming a polysilicon layer on the surface of the first conduction type region;
implanting ions of the first conduction type, to form at least two JFET sources in the JFET region, and form a power device source in the power device region;
photoetching and etching to remove polysilicon and other surface medium above a position between two adjacent JFET sources, for forming a channel implantation window, and implanting ions of the first conduction type into the channel implantation window, for forming a lateral channel region; and
photoetching and etching a contact holes, depositing a metal layer, filling the metal layer into the contact hole, to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the power device source respectively;
wherein the forming the plurality of first wells within the first conduction type region comprises: forming a first well at a boundary between the JFET region and the power device region, as isolation of the JFET region and the power device region;
after the forming the polysilicon layer on the surface of the first conductive type region, the method further comprising: implanting ions of the second conduction type into the first conductive type region and forming a plurality of second wells by driving-in, while the second wells located within the JFET region are respectively formed within different first wells; and an ion concentration of the each second well is greater than that of the each first well.

10. The method according to claim 9 , wherein the step of forming the JFET sources in the JFET region and forming the power device source in the power device region is: implanting ions of the first conduction type into the second wells to respectively form the JFET source in the JFET region and the power device source in the power device region.

11. The method according to claim 9 , wherein after the step of forming the JFET sources in the JFET region and forming the power device source in the power device region, and prior to the step of photoetching and etching to remove the polysilicon and other surface medium above the position between the two adjacent JFET sources for forming the channel implantation window, further comprises: a step of implanting ions of the second conduction type into the second well of the power device region, to form an unclamped inductive switching region under the power device source and the JFET source within the second well, while an implantation energy is greater than that of the step of implanting ions of the first conduction type.

12. The method according to claim 11 , wherein after the step of forming the JFET sources in the JFET region and forming the power device source in the power device region, and prior to the step of implanting ions of the second conduction type into the second well of the power device region, further comprises: a step of forming an implantation barrier layer.

13. The method according to claim 9 , wherein the first conduction type is an N type, the second conduction type is a P type, the first conduction type region is an N type epitaxial layer, and the power device is a Vertical Double-diffused Metal-Oxide-Semiconductor Fiel

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Gu Yan
• Cheng Shikang
• Zhang Sen

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D84/0156

  Manufacturing their doped wells · CPC title

• H10D84/0133

  Manufacturing common source or drain regions between multiple IGFETs · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title