Apparatus, method, and system for ensuring quality of service for multi-threading processor cores

Patent metadata

Field	Value
Publication number	US-10866834-B2
Application number	US-201916370248-A
Country	US
Kind code	B2
Filing date	Mar 29, 2019
Priority date	Mar 29, 2019
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

First claim

What is claimed is:

1. A simultaneous multi-threading (SMT) processor core comprising:
priority controller circuitry to access class of service (CLOS)-to-priority maps to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core based on a CLOS value assigned to each thread, the priority controller circuitry further to generate a priority vector comprising the thread priority value of each of the plurality of threads; and
thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector, wherein a thread with a higher priority value is assigned a larger portion of the execution cycles and a thread with a lower priority value is assigned a smaller portion of the execution cycles, and threads having a same priority value are assigned a same size portion of the execution cycles, the thread selector circuitry further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

2. The SMT processor core of claim 1 , wherein during a first execution cycle assigned to a first thread, tasks from the first thread will always be selected by the thread selector circuitry for processing by the pipeline before tasks from other threads are selected, so long as there are tasks from the first thread ready for processing by the pipeline.

3. The SMT processor of claim 2 , wherein when the first thread has no tasks ready for processing by the pipeline, the first execution cycle is reassigned to another thread of the plurality of threads.

4. The SMT processor of claim 3 , wherein if the first thread is associated with a lowest priority value, the first execution cycle which was is reassigned to another thread of the plurality of threads.

5. The SMT processor of claim 4 , wherein the first execution cycle is reassigned to another thread based on a least recently used (LRU) or a round robin policy.

6. The SMT processor of claim 4 , wherein the first execution cycle is reassigned to another thread having a same or higher priority value as the first thread, and when there is no thread having the same or higher priority value as the first thread, the first execution cycle is reassigned to another thread having a next highest priority value after the first thread.

7. The SMT processor core of claim 1 , wherein the pipeline comprises one of instruction decode pipeline, branch prediction pipeline, execution pipeline, and retirement pipeline.

8. The SMT processor core of claim 1 , further comprising resource allocation circuitry to assign a portion of a resource to each of the plurality of threads and to assign all remaining portion of the resource to one or more threads having a highest priority value among the thread priority values in the priority vector.

9. The SMT processor core of claim 8 , wherein the resource comprises entries in an execution reservation station.

10. A method implemented with a processing system comprising at least one processor having thereon memory-stored instructions which, when executed by the processor, cause the processor to perform the method, comprising:
accessing class of service (CLOS)-to-priority maps to determine a thread priority value for each of a plurality of threads to be executed by a simultaneous multi-threading (SMT) processor core based on a CLOS value assigned to each thread;
generating a priority vector comprising the thread priority value of each of the plurality of threads;
making execution cycle assignments for a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector, wherein a thread with a higher priority value is assigned a larger portion of the execution cycles and a thread with a lower priority value is assigned a smaller portion of the execution cycles, and threads having a same priority value are assigned a same size portion of the execution cycles; and
selecting, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

11. The method of claim 10 , further comprising selecting from a first thread tasks that are ready for execution before selecting tasks from other threads during a first execution cycle assigned to the first thread.

12. The method of claim 11 , further comprising determining that the first thread has no task ready for execution by the pipeline in the first execution cycle or that the first thread is associated with a lowest priority value, and responsively reassigning the first execution cycle to another thread of the plurality of threads.

13. The method of claim 12 , further comprising reassigning the first execution cycle to another thread of the plurality of threads based on a least recently used (LRU) or a round robin policy.

14. The method of claim 12 , further comprising reassigning the first execution cycle to another thread having a same or higher priority value as the first thread, and reassigning the first execution cycle to another thread having a next highest priority value after the first thread when there is no thread having the same or higher priority value as the first thread.

15. The method of claim 10 , wherein the pipeline comprises one of instruction decode pipeline, branch prediction pipeline, execution pipeline, or retirement pipeline.

16. The method of claim 10 , further comprising:
assigning a portion of a resource to each of the plurality of threads; and
assigning all remaining portion of the resource to one or more threads having a highest priority value among the thread priority values in the priority vector.

17. The method of claim 16 , wherein the resource comprises entries in an execution reservation station.

18. A system comprising:
a simultaneous multi-threading (SMT) processor core;
storage to store one or more class of service (CLOS) assignments, each CLOS assignment corresponds to one of a plurality of threads to be executed by the SMT processor core and stores a CLOS value assigned to the corresponding thread;
one or more CLOS-to-priority maps to store a plurality of priority values, each priority value corresponding to a different one of a plurality of CLOS values;
priority controller circuitry to access the one or more CLOS-to-priority maps to determine a thread priority value for each of a plurality of threads based on a CLOS value assigned to each thread in accordance to the one or more CLOS assignments, the priority controller circuitry further to generate a priority vector comprising the thread priority value of each of the plurality of threads; and
thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector, wherein a thread with a higher priority value is assigned a larger portion of the execution cycles and a thread with a lower priority value is assigned a smaller portion of the execution cycles, and threads having a same priority value are assigned a same size portion of the execution cycles, the thread selector circuitry further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

19. The system of claim 18 , wherein during a first execution cycle assigned to a first thread of

Assignees

• Intel Corp

Inventors

• Herdrich Andrew
• Steiner Ian
• Peled Leeor
• Prinke Michael
• Toledano Eylon

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3854

  Instruction completion, e.g. retiring, committing or graduating · CPC title

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F9/382 Primary

  Pipelined decoding, e.g. using predecoding · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title