Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride

Patent metadata

Field	Value
Publication number	US-10866807-B2
Application number	US-201113977349-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions differing by a constant stride of at least two. In an aspect, storing the result including the sequence of the at least four integers is performed without calculating the at least four integers using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.

First claim

What is claimed is:

1. A method comprising:
receiving an instruction, the instruction indicating a destination storage location and specifying a register storing a single integer representing a constant stride of at least two, wherein the instruction does not have an immediate;
storing a result in the destination storage location in response to the instruction, the result including a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions differing by the constant stride of at least two,
wherein each of the at least four non-negative integers is determined based on the constant stride of at least two,
wherein storing the result including the sequence of the at least four integers is performed without calculating the at least four integers using a result of a preceding instruction, and
wherein it is fixed by an opcode of the instruction that said all integers in the consecutive positions are to differ by a constant stride.

2. The method of claim 1 , wherein receiving comprises receiving a control indexes generation instruction, and wherein storing the result comprises storing the sequence of the at least four integers as at least four corresponding control indexes.

3. The method of claim 1 , wherein it is fixed by the opcode of the instruction that said all integers in the consecutive positions are to differ by the constant stride of at least two.

4. The method of claim 1 , wherein receiving comprises receiving the instruction specifying an integer offset, and wherein storing comprises storing a smallest one of the at least four integers which differs from zero by the integer offset.

5. The method of claim 1 , wherein storing the result comprises storing the sequence of the at least four non-negative integers which are consecutive same parity integers in numerical order in the destination storage location.

6. The method of claim 1 , wherein storing the result comprises storing one of:
1, 3, 5, 7, 9, 11, 13, 15;
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31; and
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63.

7. An apparatus comprising:
a destination storage location; and
an execution unit coupled with the destination storage location, the execution unit, in response to an instruction that is to indicate the destination storage location and that does not have an immediate, to generate and store a result in the destination storage location, the result to include a sequence of at least four integers in numerical order in which all integers in consecutive positions are to differ by a constant stride of at least two,
wherein the execution unit is to generate each of the at least four integers, except for a lowest order one, from the constant stride of at least two, and
wherein it is fixed for an opcode of the instruction that said all integers in the consecutive positions are to differ by the constant stride of at least two.

8. The apparatus of claim 7 , wherein the instruction comprises a control indexes generation instruction, and wherein the execution unit, in response to the instruction, is to store the sequence of the at least four integers as at least four corresponding control indexes.

9. The apparatus of claim 7 , wherein the instruction is to specify the constant stride of at least two.

10. The apparatus of claim 7 , wherein the instruction is to specify an integer offset, and wherein the execution unit is to store the lowest order one of the at least four integers which is to differ from zero by the integer offset.

11. The apparatus of claim 7 , wherein the instruction is to indicate the constant stride of at least two and is to indicate an integer offset, and wherein the execution unit is to store the lowest order one of the at least four integers that is to differ from zero by the offset.

12. The apparatus of claim 7 , wherein the instruction is not to indicate a source operand in an architecturally-visible storage location.

13. The apparatus of claim 7 , wherein the execution unit, in response to the instruction, is to store the sequence of the at least four integers which are to be consecutive same parity integers in the numerical order.

14. The apparatus of claim 7 , wherein the execution unit, in response to the instruction, is to store as the result one of:
0, 2, 4, 6, 8, 10, 12, 14;
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30; and
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62.

15. The apparatus of claim 7 , wherein the execution unit, in response to the instruction, is to store the sequence of at least eight integers in the numerical order with all integers in consecutive positions to differ by the constant stride of at least two.

16. The apparatus of claim 13 , wherein the execution unit, in response to the instruction, is to store the sequence of at least thirty-two integers in the numerical order with all integers in consecutive positions to differ by the constant stride of at least two.

17. A system comprising:
an interconnect;
a processor coupled with the interconnect, the processor including a destination register, the processor, in response to an instruction that is to indicate the destination register, that is to specify a register that is to store a single integer representing a constant stride of at least two, and that does not have an immediate, to store a result in the destination register, the result to include a sequence of at least four non-negative integers in numerical order with all integers in consecutive positions to differ by the constant stride of at least two,
wherein the processor is to determine each of the at least four non-negative integers based in part on the constant stride of at least two,
wherein the processor is to store the result in response to the instruction that does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location, and
wherein it is to be fixed for an opcode of the instruction that said all integers in the consecutive positions are to differ by a constant stride; and
a dynamic random access memory (DRAM) coupled with the interconnect.

18. The system of claim 17 , wherein the processor comprises a reduced instruction set computing (RISC) processor.

19. An article of manufacture comprising:
a non-transitory machine-readable storage medium, the machine-readable storage medium storing instructions including an instruction,
the instruction to indicate a destination storage location, and to specify a register that is to store a single integer representing a constant stride of at least two, wherein the instruction does not have an immediate, and the instruction, if executed by a machine, to cause the machine to perform operations comprising to:
determine a sequence of at least four non-negative integers in numerical order based on the constant stride of at least two; and
store a result in the destination storage location, the result to include the sequence of the at least four non-negative integers in the numerical order with all integers in consecutive positions to differ by the constant stride of at least two,
wherein the instruction is not to indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location, and
wherein it is to be fixed for an opcode of the instruction that said all integers in

Assignees

• Ould Ahmed Vall Elmoustapha
• Abraham Seth
• Valentine Robert
• Sperber Zeev
• Gradstein Amit
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Abraham Seth
• Valentine Robert
• Sperber Zeev
• Gradstein Amit

Classifications

• G06F9/30038

  using a mask · CPC title

• G06F9/30018 Primary

  Bit or string instructions · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30181 Primary

  Instruction operation extension or modification · CPC title