Phase difference generator error compensation method of digital frequency generator

Patent metadata

Field	Value
Publication number	US-10866611-B2
Application number	US-201916728238-A
Country	US
Kind code	B2
Filing date	Dec 27, 2019
Priority date	Dec 29, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

The invention provides a phase difference generator error compensation method of a digital frequency generator, wherein the digital frequency generator comprises a phase difference generator, the phase difference generator comprises a phase compensation module and an adjusting module, the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; the adjusting module compensates the error of the third clock signal according to the clock phase difference. The method has the benefits that process errors in the phase difference generator are compensated.

First claim

What is claimed is:

1. A phase difference generator error compensation method of a digital frequency generator, applied to the digital frequency generator, the digital frequency generator comprising the phase difference generator, the phase difference generator comprising a phase compensation module and an adjusting module, wherein
the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; and
the adjusting module compensates an error of the third clock signal according to the clock phase difference;
the phase difference generator comprises a phase difference circuit, the phase difference circuit provides a comparator, a non-inverting input end of the comparator is connected to a reference voltage, an inverting input end of the comparator is connected in parallel with a voltage source VDD;
the phase difference generator further comprises a first current source and a second current source;
the phase difference generator further comprises a capacitor connecting the inverting input end of the comparator to GND;
a first switch controlled by the first clock signal is connected in series between the first current source and the inverting input end of the comparator; and
a second switch controlled by the second clock signal is connected in series between the second current source and the inverting input end of the comparator;
wherein the adjusting module compensates the error of the third clock signal according to the clock phase difference by the following formula:

(

VDD
-
Vref

)

=

A
*

T
VCO

*
2
⁢
π
⁢

/

⁢

2
N

*

I
C

wherein VDD represents the voltage source VDD;
V ref represents the reference voltage;
T represents the time corresponding to the phase difference;
I represents an overall current, and the overall current is a sum of the current of the first current source and the current of the second current source;
C represents the capacitance value of the capacitor; and
A represents a ratio of the current of the first current source to the overall current.

2. The phase difference generator error compensation method of a digital frequency generator of claim 1 , wherein the clock phase difference is expressed by T VCO *2π/2 N ;
wherein T VCO represents a time when clock signals are input to a fraction divider for generating the first clock signal and the second clock signal;
2 N represents the number of the clock signals configured to generate the third clock signal.

3. The phase difference generator error compensation method of a digital frequency generator of claim 1 , wherein the adjusting module adjusts a current of the first current source, and/or a current of the second current source.

4. The phase difference generator error compensation method of a digital frequency generator of claim 1 , wherein the adjusting module adjusts a capacitance value of the capacitor, and/or a charging/discharging speed.

5. The phase difference generator error compensation method of a digital frequency generator of claim 1 , wherein the adjusting module adjusts an amplitude value of the reference voltage.

6. The phase difference generator error compensation method of a digital frequency generator of claim 1 , wherein a relationship between the current of the first current source and the current of the second current source satisfies the following formula:
A*I+B*I=I;
wherein B represents a ratio of the current of the second current source to the overall current.

7. The phase difference generator error compensation method of a digital frequency generator of claim 1 , wherein a value of the current of the first current source is in a range from 0 to I, and a value of the current of the second current source is in a range from 0 to I.

Assignees

• Amlogic Shanghai Co Ltd

Inventors

• Zou Weihua
• Shi Ming
• Wang Yan

Classifications

• H03L7/0898

  the source or sink current values being variable (H03L7/0896 takes precedence) · CPC title

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• G06F1/06 Primary

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title