Panel unit
US-2017284096-A1 · Oct 5, 2017 · US
US10866039B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10866039-B2 |
| Application number | US-201816231992-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 25, 2018 |
| Priority date | Dec 28, 2017 |
| Publication date | Dec 15, 2020 |
| Grant date | Dec 15, 2020 |
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A thermal transistor is provided. The thermal transistor includes a metallic thermal conductor, a non-metallic thermal conductor, and a thermal resistance adjusting unit. The metallic thermal conductor and the non-metallic thermal conductor are contact with each other to form a thermal interface. The thermal resistance adjusting unit is configured to generate an bias voltage U12 between the metallic thermal conductor and the non-metallic thermal conductor.
Opening claim text (preview).
What is claimed is: 1. A thermal transistor, comprising: a metallic thermal conductor, a non-metallic thermal conductor, and a thermal resistance adjusting unit; the metallic thermal conductor and the non-metallic thermal conductor are in contact with each other to form a thermal interface; wherein a material of the non-metallic thermal conductor is buckypaper with a density ranging from 1.2 g/cm 3 to 1.3 g/cm 3 ; and the thermal resistance adjusting unit is configured to generate a bias voltage U12 between the metallic thermal conductor and the non-metallic thermal conductor. 2. The thermal transistor of claim 1 , wherein a thickness of the metallic thermal conductor ranges from 0.1 mm to 1 mm. 3. The thermal transistor of claim 1 , wherein a material of the metallic thermal conductor is selected from the group consisting of copper, aluminum, iron, gold, silver, and alloy thereof. 4. The thermal transistor of claim 1 , wherein the metallic thermal conductor and the non-metallic thermal conductor are disposed in a sealed space. 5. The thermal transistor of claim 1 , wherein the metallic thermal conductor and the non-metallic thermal conductor are disposed in a vacuum environment. 6. The thermal transistor of claim 1 , wherein the bias voltage U12 ranges from −3V to 3V. 7. The thermal transistor of claim 1 , wherein the thermal resistance adjusting unit comprises a voltage source electrically connected to each of the metallic thermal conductor and the non-metallic thermal conductor; the voltage source is configured to control electric potentials between the metallic thermal conductor and the non-metallic thermal conductor. 8. The thermal transistor of claim 7 , wherein the thermal resistance adjusting unit further comprises: a first control unit electrically connected to the voltage source, the first control unit comprises a memory storing a mapping table of the bias voltage U12 versus interfacial thermal resistance. 9. The thermal transistor of claim 1 , wherein the metallic thermal conductor comprises a first surface and a second surface; the non-metallic thermal conductor comprises a third surface and a fourth surface; the first surface and the third surface are in direct contact with each other to form the thermal interface. 10. The thermal transistor of claim 9 , wherein each of the second surface and the fourth surface is thermally connected to a heat source or thermal device.
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