Dual ramp modulation for a switch-mode power supply

Patent metadata

Field	Value
Publication number	US-10862397-B2
Application number	US-201816160697-A
Country	US
Kind code	B2
Filing date	Oct 15, 2018
Priority date	Jul 17, 2017
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A switch-mode power supply includes a transformer, a power transistor, pulse generation circuitry, and a dual ramp modulation (DRM) circuit. The power transistor is coupled to a primary coil of the transformer. The pulse generation circuitry is configured to generate a power transistor activation signal. The DRM circuit is coupled to the pulse generation circuitry. The DRM circuit is configured to generate a leading edge blank time signal that disables inactivation of the power transistor activation signal for a predetermined interval (a leading edge blank time) after a leading edge of the power transistor activation signal. The DRM circuit is also configured to generate a reset signal that inactivates the power transistor activation signal while the leading edge blank time signal is activated.

First claim

What is claimed is:

1. A switch-mode power supply controller, comprising:
pulse generation circuitry having a blanking input, a reset input, and a power transistor drive output;
voltage clamping circuitry having an output coupled to an optical coupler voltage input, and having a clamped voltage output;
a voltage comparator having a drive voltage input, an output voltage input, and a compare output; and
a dual ramp modulation (DRM) circuit having a compare input coupled to the compare output, having a clamped voltage input coupled to the clamped voltage output, having a blanking output coupled to the blanking input, and having a reset output coupled to the reset input.

2. The switch-mode power supply controller of claim 1 , in which the DRM circuit includes:
ramp circuitry having an input coupled to the power transistor drive output and having a voltage ramp output;
timer circuitry including a flip-flop with a set input coupled to the power transistor drive input, a reset input, and an output coupled to the blanking output, and including a timer comparator having an input coupled to the voltage ramp output, having an reference voltage input, and an output coupled to the reset input of the flip-flop.

3. The switch-mode power supply controller of claim 2 , in which the DRM circuit includes:
reset circuitry including a detector flip-flop having an input coupled to the compare input, a clock input coupled to the blanking output, and an enable output;
a reset comparator having an input coupled to the voltage ramp output, an input coupled to the clamped voltage input, and an output; and
gating circuitry having an input coupled to the enable output, an input coupled to the output of the reset comparator, and an output coupled to the reset output.

4. The switch-mode power supply controller of claim 1 in which the power transistor drive output is a pulse width modulator low output.

5. A power supply controller, comprising:
a dual ramp modulation (DRM) circuit including:
a ramp generator configured to generate a ramp signal based on a pulse width modulation (PWM) signal;
a first comparator having a non-inverting input coupled to receive the ramp signal, an inverting input coupled to receive a leading edge blank time (LEB) reference voltage, and a first comparator output; and
a second comparator having a non-inverting input coupled to receive the ramp signal, an inverting input coupled to receive an adjusted LEB reference voltage offset from the LEB reference voltage by a feedback voltage, and a second comparator output.

6. The power supply controller of claim 5 , in which the DRM circuit includes:
a set-reset flip flop having a set input coupled to receive the PWM signal, a reset input coupled to the first comparator output, and an LEB output.

7. The power supply controller of claim 6 , in which the DRM circuit includes:
an adjustment circuit having a feedback voltage input, an LEB reference voltage input, and an output providing the adjusted LEB reference voltage; and
an AND gate having an input coupled to the second comparator output, and an output configured to deliver a reset signal.

8. The power supply controller of claim 7 , including:
pulse generation circuitry configured to generate the PWM signal including a rising edge and a falling edge, the pulse generation circuitry configured to delay the falling edge based on the LEB signal, and configured to inhibit the LEB signal based on the reset signal.

9. A switch mode power supply controller comprising:
driver circuitry having a driver pulse width modulated input, and a drive output adapted to be coupled to a control terminal of a power transistor; and
pulse generation circuitry including:
a current sense comparator having a current sense voltage input, an optical coupler voltage input, and current sense output;
gating circuitry having a current sense input coupled to the current sense output, a blanking input, a reset input, and a gated pulse width modulated output coupled to the driver pulse width modulated input;
clamping circuitry having an output coupled to the optical coupler voltage input, and having a clamped voltage output; and
dual ramp modulation circuitry having a dual ramp pulse width modulated input coupled to the gated pulse width modulate output, having a current sense input coupled to the current sense output, having a clamped voltage input coupled to the clamped voltage output, having a blanking output coupled to the blanking input, and having a reset output coupled to the reset input.

10. The switch-mode power supply controller of claim 9 in which the clamping circuitry includes:
a reference voltage source having a terminal coupled to circuit ground and another terminal;
a diode having an anode coupled to the another terminal and a cathode coupled to the optical coupler voltage input; and
the clamped voltage output being coupled between the another terminal and the anode.

11. The switch-mode power supply controller of claim 9 in which the dual ramp modulation circuitry includes ramp generator circuitry, the ramp generator circuitry including:
logic having an input coupled to the dual ramp pulse width modulated input, and having a switch output;
a switch having a control terminal coupled to the switch output, a first terminal, and a second terminal;
a capacitor having a first terminal coupled to circuit ground and to the first terminal of the switch, and having a second terminal coupled to the second terminal of the switch; and
a current source having a source terminal coupled to the second terminal of the capacitor and the second terminal of the switch, the source terminal forming a ramp generator output.

12. The switch-mode power supply controller of claim 9 in which the dual ramp modulation circuitry includes timer circuitry, the timer circuitry including:
a timer comparator having a reference voltage input, a ramp generator input and an output; and
a timer flip-flop having a set input coupled to the dual ramp pulse width modulated input, having a reset input coupled to the output of the comparator, and having a timer output.

13. The switch-mode power supply controller of claim 9 in which the dual ramp modulation circuitry includes reset circuitry, the reset circuitry including:
a reset flip flop having a clock input, a current sense input, and an enable output;
a comparator having a ramp generator input, a clamped voltage input, and a comparator output; and
a logic gate having a comparator input coupled to the comparator output, an enable input coupled to the enable output, and a reset output.

Assignees

• Texas Instruments Inc

Inventors

• Liu Pei-Hsin
• Valley Richard Lee

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• H02M1/0038

  Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control · CPC title

• H02M3/33507

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title