Pixel structure

US10861882B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10861882-B2
Application numberUS-201916512416-A
CountryUS
Kind codeB2
Filing dateJul 16, 2019
Priority dateJul 18, 2018
Publication dateDec 8, 2020
Grant dateDec 8, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel structure includes a first TFT, an adhesive layer, an LED, and a detection conductive layer. The first TFT is coupled to a conductive layer and is configured to transmit display data to the conductive layer. The adhesive layer covers the conductive layer. The LED is disposed on the adhesive layer. The detection conductive layer is disposed on the adhesive layer, and the detection conductive layer, the adhesive layer, and the conductive layer constitute a detection capacitor. Here, a thickness of the detection conductive layer is equal to or slightly greater than a height of the LED.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel structure comprising: a first thin film transistor having a first terminal coupled to a conductive layer and configured to transmit display data to the conductive layer; an adhesive layer disposed on the conductive layer; a light emitting diode disposed on the adhesive layer; and a detection conductive layer disposed on the adhesive layer, wherein the detection conductive layer, the adhesive layer, and the conductive layer constitute a detection capacitor, wherein a thickness of the detection conductive layer is equal to or slightly greater than a height of the light emitting diode. 2. The pixel structure according to claim 1 , wherein when a stamping process is performed on the pixel structure, an upper surface of the light emitting diode and an upper surface of the detection conductive layer together receive a same stamping force. 3. The pixel structure according to claim 1 , further comprising: a second thin film transistor, wherein a control terminal of the second thin film transistor is coupled to the conductive layer, a first terminal of the second thin film transistor receives a reference voltage, and a second terminal of the second thin film transistor is coupled to the light emitting diode. 4. The pixel structure according to claim 3 , wherein a control terminal of the first thin film transistor receives a scan signal, and the detection conductive layer receives a detection signal, wherein in a first time period the first thin film transistor is turned on according to the scan signal and transmits the display data to the control terminal of the second thin film transistor, and the detection conductive layer simultaneously receives the detection signal at a first voltage level, and in a second time period after the first time period, the first thin film transistor is turned off according to the scan signal, the detection conductive layer simultaneously receives the detection signal at a second voltage level, wherein the first voltage level is different from the second voltage level. 5. The pixel structure according to claim 4 , wherein the scan signal and the detection signal are identical signal. 6. The pixel structure according to claim 4 , wherein when the first thin film transistor and the second thin film transistor are both p-type thin film transistors, the first voltage level is lower than the second voltage level, and the reference voltage is a first power voltage. 7. The pixel structure according to claim 4 , wherein when the first thin film transistor and the second thin film transistor are both n-type thin film transistors, the first voltage level is higher than the second voltage level, and the reference voltage is a second power voltage. 8. The pixel structure according to claim 3 , wherein the detection conductive layer is coupled to the first terminal of the second thin film transistor. 9. The pixel structure according to claim 8 , wherein the second terminal of the first thin film transistor receives an initial voltage or the display data, wherein when the first thin film transistor is switched on, the first thin film transistor sequentially receives and transmits the initial voltage and the display data to the control terminal of the second thin film transistor. 10. The pixel structure according to claim 8 , further comprising: a third thin film transistor, one terminal of the third thin film transistor receiving an initial voltage, the other terminal of the third thin film transistor being coupled to the control terminal of the second thin film transistor, the third thin film transistor being controlled by a pre-scan signal and being switched on or off. 11. The pixel structure according to claim 3 , further comprising: a storage capacitor coupled between the control terminal and the first terminal of the second thin film transistor. 12. The pixel structure according to claim 3 , wherein the second thin film transistor generates a driving current to drive the light emitting diode, and a capacitance of the driving current and a capacitance of the detection capacitor are negatively correlated.

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • characterised by multiple passive components, e.g. resistors, capacitors or inductors · CPC title

  • integrated with passive devices, e.g. auxiliary capacitors · CPC title

  • H10D86/60Primary

    wherein the TFTs are in active matrices · CPC title

  • H10F39/803Primary

    Pixels having integrated switching, control, storage or amplification elements · CPC title

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What does patent US10861882B2 cover?
A pixel structure includes a first TFT, an adhesive layer, an LED, and a detection conductive layer. The first TFT is coupled to a conductive layer and is configured to transmit display data to the conductive layer. The adhesive layer covers the conductive layer. The LED is disposed on the adhesive layer. The detection conductive layer is disposed on the adhesive layer, and the detection conduc…
Who is the assignee on this patent?
Au Optronics Corp
What technology area does this patent fall under?
Primary CPC classification H10D86/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 08 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).