Methods for forming structurally-reinforced semiconductor plug in three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-10861868-B2
Application number	US-201816140468-A
Country	US
Kind code	B2
Filing date	Sep 24, 2018
Priority date	Aug 16, 2018
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

Embodiments of 3D memory devices with a structurally-reinforced semiconductor plug and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack is formed on a substrate. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. An opening extending vertically through the dielectric stack is formed. A shallow recess is formed by removing a part of a sacrificial layer abutting a sidewall of the opening. The sacrificial layer is at a lower portion of the dielectric stack. A semiconductor plug is formed at a lower portion of the opening. A part of the semiconductor plug protrudes into the shallow recess. A channel structure is formed above and in contact with the semiconductor plug in the opening. A memory stack including a plurality of conductor/dielectric layer pairs is formed by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric stack.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack on a substrate, the dielectric stack comprising a plurality of interleaved dielectric layers and sacrificial layers, the sacrificial layers each being deposited under a same deposition condition;
forming an opening extending vertically through the dielectric stack;
forming a shallow recess by removing a part of a sacrificial layer abutting a sidewall of the opening, the sacrificial layer being at a lower portion of the dielectric stack;
forming a semiconductor plug at a lower portion of the opening, wherein a part of the semiconductor plug protrudes into the shallow recess;
forming a channel structure above and in contact with the semiconductor plug in the opening;
removing the protruding part of the semiconductor plug; and
forming a memory stack comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric stack.

2. The method of claim 1 , wherein after removing the protruding part of the semiconductor plug, a lateral dimension of the semiconductor plug becomes substantially the same along a vertical direction.

3. The method of claim 2 , wherein removing the protruding part of the semiconductor plug comprises an etching process.

4. The method of claim 2 , wherein a variation of the lateral dimension of the semiconductor plug along the vertical direction is less than 25% after removing the protruding part of the semiconductor plug.

5. The method of claim 1 , wherein the substrate comprises silicon, and each of the sacrificial layers comprises silicon nitride.

6. The method of claim 5 , wherein forming the shallow recess comprises applying, through the opening, an etchant having a selectivity between silicon nitride and silicon oxide that is greater than 1.

7. The method of claim 6 , wherein the etchant comprises hydrofluoric acid and ozone.

8. The method of claim 7 , where a weight ratio of hydrofluoric acid to ozone is between about 1:10 and about 1:50.

9. The method of claim 1 , wherein forming the semiconductor plug comprises epitaxially growing a semiconductor layer from the substrate in the opening.

10. The method of claim 1 , wherein forming the channel structure comprises:
forming a memory film along the sidewall of the opening above the semiconductor plug; and
forming a semiconductor channel extending vertically over the memory film.

11. The method of claim 1 , wherein forming the memory stack comprises:
forming a slit through the dielectric stack;
etching the sacrificial layers in the dielectric stack through the slit to form a plurality of lateral recesses;
depositing gate dielectric layers along sidewalls of the slit and the lateral recesses; and
depositing the conductor layers over the gate dielectric layers.

12. The method of claim 11 , wherein etching the sacrificial layers comprises applying an etchant comprising phosphoric acid through the opening.

13. A method for forming a semiconductor structure, comprising:
forming a plurality of interleaved dielectric layers and sacrificial layers on a substrate;
forming an opening extending vertically through the interleaved dielectric layers and sacrificial layers;
forming a shallow recess by removing a part of one of the sacrificial layers abutting a sidewall of the opening;
forming a semiconductor plug at a lower portion of the opening, wherein a part of the semiconductor plug protrudes into the shallow recess;
trimming the protruding part of the semiconductor plug such that a lateral dimension of the semiconductor plug becomes substantially the same along a vertical direction; and
removing the sacrificial layers during the trimming of the protruding part of the semiconductor plug.

14. The method of claim 13 , wherein the substrate comprises silicon, and each of the sacrificial layers comprises silicon nitride.

15. The method of claim 14 , wherein forming the shallow recess comprises applying, through the opening, an etchant having a selectivity between silicon nitride and silicon oxide ranging from about 1 to about 50.

16. The method of claim 15 , wherein the etchant comprises hydrofluoric acid and ozone.

17. The method of claim 13 , wherein forming the semiconductor plug comprises epitaxially growing a semiconductor layer from the substrate in the opening.

18. A method for forming a semiconductor structure, comprising:
forming a plurality of interleaved dielectric layers and sacrificial layers on a substrate;
forming an opening extending vertically through the interleaved dielectric layers and sacrificial layers;
forming a shallow recess by removing a part of one of the sacrificial layers, abutting a sidewall of the opening;
forming a semiconductor plug at a lower portion of the opening, wherein a part of the semiconductor plug protrudes into the shallow recess; and
trimming the protruding part of the semiconductor plug by etching away the protruding part such that a lateral dimension of the semiconductor plug becomes substantially the same along a vertical direction.

19. The method of claim 18 , wherein forming the shallow recess comprises applying, through the opening, an etchant having a selectivity between silicon nitride and silicon oxide ranging from about 1 to about 50.

20. The method of claim 19 , wherein the selectivity of the etchant ranges from about 1 to about 5.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Jiang Yangbo
• Wu liang hui
• Wang Ya Jun
• Zhang Jingping

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title

• H01L21/76802

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic