Sense amplifier with increased headroom

Patent metadata

Field	Value
Publication number	US-10861507-B2
Application number	US-201916368311-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Mar 28, 2019
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.

First claim

What is claimed is:

1. A circuit comprising:
a first differential stack wherein each leg of the first differential stack is connected to a drain of a common tail transistor; and
a second differential stack comprising a first leg and a second leg;
wherein the circuit is configured to:
receive a first input signal on a gate of a first transistor in the first leg of the second differential stack;
receive a second input signal on a gate of a first transistor in the second leg of the second differential stack;
precharge first and second differential output nodes while simultaneously amplifying a difference between the first input signal and the second input signal when a received clock signal has a first value;
stop precharging the first and second differential output nodes when the received clock signal has a second value; and
amplify the difference between the first input signal and the second input signal to generate an output signal by turning on the common tail transistor when the received clock signal has the second value, wherein the output signal is generated on the first and second differential output nodes.

2. The circuit as recited in claim 1 , wherein the circuit is further configured to:
receive the received clock signal on a gate of the common tail transistor; and
receive an inverted clock signal on each gate of a pair of transistors on each leg of the second differential stack.

3. The circuit as recited in claim 1 , wherein the first differential stack comprises a first plurality of transistors connected in series between a supply voltage and ground, wherein the first plurality of transistors form a cross-coupled pair of inverters, and wherein the second differential stack comprises a second plurality of transistors connected in series between the first and second differential output nodes and ground.

4. The circuit as recited in claim 3 , wherein each leg of the first differential stack consists of three transistors in between the supply voltage and ground.

5. The circuit as recited in claim 4 , wherein one of the three transistors is the common tail transistor.

6. The circuit as recited in claim 5 , wherein a source of the common tail transistor is connected to ground.

7. The circuit as recited in claim 1 , wherein the circuit is part of a sense amplifier.

8. A method comprising:
receiving a clock signal on a gate of a common tail transistor of a first differential stack, wherein each leg of the first differential stack is connected to the drain of the common tail transistor;
receiving a first input signal on a gate of a first transistor in a first leg of a second differential stack;
receiving a second input signal on a gate of a first transistor in a second leg of the second differential stack;
precharging first and second differential output nodes while simultaneously amplifying a difference between the first input signal and the second input signal when the clock signal has a first value;
stopping precharging the first and second differential output nodes when the clock signal has a second value; and
amplifying the difference between the first input signal and the second input signal to generate an output signal by turning on the common tail transistor when the clock signal has the second value, wherein the output signal is generated on the first and second differential output nodes.

9. The method as recited in claim 8 , further comprising receiving an inverted clock signal on each gate of a pair of transistors on each leg of the second differential stack.

10. The method as recited in claim 8 , wherein the first differential stack comprises a first plurality of transistors connected in series between a supply voltage and ground, wherein the first plurality of transistors form a cross-coupled pair of inverters, and wherein the second differential stack comprises a second plurality of transistors connected in series between the first and second differential output nodes and ground.

11. The method as recited in claim 10 , wherein each leg of the first differential stack consists of three transistors in between the supply voltage and ground.

12. The method as recited in claim 11 , wherein one of the three transistors is the common tail transistor.

13. The method as recited in claim 12 , wherein a source of the common tail transistor is connected to ground.

14. The method as recited in claim 8 , further comprising amplifying the difference between the first input signal and the second input signal to generate an output signal as part of a sense amplifier.

15. A circuit comprising:
a cross-coupled pair of state nodes; and
a plurality of transistors;
wherein the circuit is configured to:
receive a first input signal on a gate of a first transistor of the plurality of transistors;
receive a second input signal on a gate of a second transistor of the plurality of transistors;
receive an inverted clock signal on each gate of a first pair of transistors of the plurality of transistors connected in series between a source of the first transistor and ground;
receive the inverted clock signal on each gate of a second pair of transistors of the plurality of transistors connected in series between a source of the second transistor and ground;
precharge the cross-coupled pair of state nodes while simultaneously amplifying a difference between the first input signal and the second input signal when the received clock signal has a first value; and
turn on a tail transistor to amplify the difference between the first input signal and the second input signal to generate an output signal on the cross-coupled pair of state nodes when the received clock signal has a second value.

16. The circuit as recited in claim 15 , wherein the circuit is further configured to receive the received clock signal on a gate of the tail transistor.

17. The circuit as recited in claim 15 , wherein a source of the first transistor is coupled to a drain of a first given transistor of the first pair of transistors, and wherein a source of the second transistor is coupled to a drain of a second given transistor of the second pair of transistors.

18. The circuit as recited in claim 15 , wherein each leg of the first differential stack consists of three transistors in between a supply voltage and ground.

19. The circuit as recited in claim 18 , wherein one of the three transistors is the tail transistor.

20. The circuit as recited in claim 15 , wherein the drain of the first transistor is connected to a drain of a first N-type transistor of the cross-coupled pair of state nodes, and wherein the drain of the second transistor is connected to a drain of a second N-type transistor of the cross-coupled pair of state nodes.

Assignees

• Advanced Micro Devices Inc

Inventors

• Paraschou Milam
• Cooper Jeffrey

Classifications

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/1087

  Data input latches · CPC title