Integrity monitor peripheral for microcontroller and processor input/output pins

Patent metadata

Field	Value
Publication number	US-10860408-B2
Application number	US-201815970159-A
Country	US
Kind code	B2
Filing date	May 3, 2018
Priority date	May 3, 2018
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.

First claim

The invention claimed is:

1. A semiconductor die, comprising:
an output pin;
a first feedback path communicatively coupled to the output pin;
an integrity monitor circuit (IMC) configured to:
receive a data value;
receive a first measured data value through the first feedback path;
compare the data value and the first measured data value; and
based on the comparison of the data value and the first measured data value, determine whether an error has occurred;

a second feedback path communicatively coupled to the output pin through a semiconductor package pin and to the IMC;
wherein the IMC is further configured to:
receive a second measured data value from the output pin routed through the second feedback path;
compare the data value and the second measured data value; and
based on the comparison of the data value and the second measured data value, determine that an error has occurred between the semiconductor die and a semiconductor package including the semiconductor die.

2. The semiconductor die of claim 1 , further comprising a logic to generate the data value, wherein:
the output pin is configured to output values from the semiconductor die, the output pin communicatively coupled to the logic; and
the data value is received from the logic.

3. The semiconductor die of claim 1 , wherein:
the comparison yields an indication that an error has occurred; and
the IMC is further configured to ignore the indication that the error has occurred based upon timing of an expected response.

4. The semiconductor die of claim 1 , wherein the IMC is further configured determine, based on the comparison of the data value and the first measured data value, that the error has occurred within the semiconductor die between logic that generated the data value and the output pin.

5. The semiconductor die of claim 1 , wherein the IMC is further configured to determine that a bond wire failure has occurred between the semiconductor die and the semiconductor package based on the comparison of the data value and the second measured data value.

6. The semiconductor die of claim 1 , wherein the IMC is further configured to determine that an error has occurred outside the semiconductor die based on the comparison of the data value and the first measured data value.

7. A semiconductor die, comprising:
an output pin;
a first feedback path communicatively coupled to the output pin;
an integrity monitor circuit (IMC) configured to:
receive a data value;
receive a first measured data value through the first feedback path;
compare the data value and the first measured data value; and
based on the comparison of the data value and the first measured data value,

determine whether an error has occurred;
a second feedback path communicatively coupled to the output pin through a semiconductor package pin and to the IMC; and
a third feedback path communicatively coupled to the output pin through an external integrated circuit pin and to the IMC;
wherein the IMC is further configured to:
receive a second measured data value from the output pin routed through the second feedback path;

compare the data value and the second measured data value;
based on the comparison of the data value and the second measured data value, determine that an error has occurred between the semiconductor die and the semiconductor package;
receive a third measured data value from the output pin routed through the third feedback path;

compare the data value and the third measured data value; and
based on the comparison of the data value and the third measured data value, determine that an error has occurred between the semiconductor package and the external integrated circuit pin.

8. An integrated circuit device, comprising:
a semiconductor die;
a semiconductor output pin;
a first feedback path communicatively coupled to the semiconductor output pin;
an integrity monitor circuit (IMC) configured to:
receive a data value;
receive a first measured data value from the semiconductor output pin routed through the first feedback path;
compare the data value and the first measured data value; and
based on the comparison of the data value and the first measured data value, determine whether an error has occurred;

a semiconductor package including a semiconductor package pin and the semiconductor die;
a second feedback path communicatively coupled to the semiconductor output pin through a semiconductor package pin and to the IMC;
wherein the IMC is further configured to:
receive a second measured data value routed through the second feedback path;
compare the data value and the second measured data value; and
based on the comparison of the data value and the second measured data value, determine that an error has occurred between the semiconductor die and the semiconductor package.

9. The integrated circuit device of claim 8 , further comprising:
a logic configured to generate the data value; and
a semiconductor output pin configured to output values from the semiconductor die, the semiconductor output pin communicatively coupled to the logic.

10. The integrated circuit device of claim 8 , wherein:
the comparison yields an indication that an error has occurred; and
the IMC is further configured to ignore the indication that the error has occurred based upon timing of an expected response.

11. The integrated circuit device of claim 8 , wherein the IMC is further configured determine, based on the comparison of the data value and the first measured data value, that the error has occurred within the semiconductor die between logic that generated the data value and the semiconductor output pin.

12. The integrated circuit device of claim 8 , wherein the IMC is further configured to determine that a bond wire failure has occurred between the semiconductor die and the semiconductor package based on the comparison of the data value and the second measured data value.

13. The integrated circuit device of claim 8 , wherein the IMC is further configured to determine that an error has occurred outside the semiconductor die based on the comparison of the data value and the first measured data value.

14. An integrated circuit device, comprising:
a semiconductor die;
a first feedback path communicatively coupled to a semiconductor output pin;
an integrity monitor circuit (IMC) configured to:
receive a data value;
receive a first measured data value from the semiconductor output pin routed through the first feedback path;
compare the data value and the first measured data value; and

based on the comparison of the data value and the first measured data value, determine whether an error has occurred;
a semiconductor package including a semiconductor package pin and the semiconductor die;
a second feedback path communicatively coupled to the semiconductor output pin through a semiconductor package pin and to the IMC; and
a third feedback path communicatively coupled to the semiconductor output pin through an external integrated circuit pin and to the IMC;
wherein the IMC is further configured to:
receive a second measured data value routed through the second feedback path;

compare the data value and the second measured data value;
based on the comparison of the second data value and the second measured data value, determine that an error has occurred between the semiconductor die and the semiconductor package;
receive a third measured data value routed through the third feedback path;

compare the data value and the third measured data value; and
based on the comparison of the data value and the third measured data

Assignees

• Microchip Tech Inc

Inventors

• Bowling Stephen
• Wojewoda Igor
• Balu Manivannan

Classifications

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G01R31/66

  Testing of connections, e.g. of plugs or non-disconnectable joints (testing for incorrect line connections G01R31/55) · CPC title

• G01R31/2853 Primary

  Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66) · CPC title

• G01R31/31717

  Interconnect testing (by scan techniques see G01R31/31855) · CPC title