Semiconductor device, electronic control unit and vehicle apparatus

Patent metadata

Field	Value
Publication number	US-10859624-B2
Application number	US-201615366985-A
Country	US
Kind code	B2
Filing date	Dec 1, 2016
Priority date	Dec 24, 2015
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor chip and a second semiconductor chip mounted on one package; and
a load driving terminal,
wherein the first semiconductor chip includes:
a power-supply transistor for supplying power to a load through the load driving terminal;
a driver circuit for driving the power-supply transistor;
a first terminal;
a current detecting resistor coupled to the first terminal so as to output a voltage in accordance with a flowing current to the first terminal;
an abnormality detection circuit for detecting an abnormality; and
a current generation circuit for generating a sense current on which a current flowing through the load driving terminal is reflected and a fault current indicating that the abnormality detection circuit has detected the abnormality so that the current generation circuit selects either the sense current or the fault current from the current generation circuit to flow through the current detecting resistor in accordance with presence or absence of detection of the abnormality, and

the second semiconductor chip includes:
a second terminal to be coupled to the first terminal;
a first analog-digital conversion circuit for converting an analog signal to be input to the second terminal into a first digital signal;
a storage circuit for storing a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value; and
an arithmetic processing circuit that sets a standard range based on the determination reference value, and determines the presence or absence of the detection of the abnormality in the abnormality detection circuit based on whether or not a current value indicated by the first digital signal is included within the standard range,

wherein the current generation circuit includes a variable current source and a constant current source, the variable current source allows the current to flow to the current detecting resistor through the first terminal, and the constant current supply allows a current to flow to the current detecting resistor through the first terminal.

2. The semiconductor device according to claim 1 ,
wherein the storage circuit stores a first determination reference value that is the determination reference value at a first temperature and a second determination reference value that is the determination reference value at a second temperature different from the first temperature, and
the arithmetic processing circuit sets a range between the first determination reference value and the second determination reference value as the standard range.

3. The semiconductor device according to claim 2 ,
wherein the arithmetic processing circuit determines the presence or absence of the detection of the abnormality based on whether or not the current value indicated by the first digital signal is continuously included within the standard range for a predetermined period.

4. The semiconductor device according to claim 2 ,
wherein the first semiconductor chip further includes:
a temperature sensor circuit for detecting a temperature; and
a third terminal for outputting a temperature monitor signal from the temperature sensor circuit,

the second semiconductor chip further includes:
a fourth terminal to be coupled to the third terminal; and
a second analog-digital conversion circuit for converting an analog signal to be input to the fourth terminal into a second digital signal, and

the storage circuit further stores a first signal level indicating a level of the temperature monitor signal at the first temperature and a second signal level indicating a level of the temperature monitor signal at the second temperature obtained in the inspection process of the semiconductor device, and
the arithmetic processing circuit sets the standard range based on the second digital signal, the first determination reference value, the first signal level, the second determination reference value and the second signal level stored in the storage circuit.

5. The semiconductor device according to claim 1 ,
wherein an inrush current flows through the load at an initial stage when power supply is started, and
the arithmetic processing circuit determines the presence or absence of the detection of the abnormality at the initial stage.

6. The semiconductor device according to claim 5 ,
wherein the current generation circuit generates a first fault current indicating that the abnormality detection circuit has detected a first abnormality, and a second fault current indicating that the abnormality detection circuit has detected a second abnormality different from the first abnormality in a type and having a current value different from a current value of the first fault current, and allows either the first fault current or the second fault current to flow through the current detecting resistor in accordance with the type of the abnormality, and
the storage circuit stores the current value of the first fault current and the current value of the second fault current obtained in the inspection process of the semiconductor device as a first abnormality determination reference value and a second abnormality determination reference value, respectively, and
the arithmetic processing circuit sets a first standard range based on the first abnormality determination reference value and a second standard range based on the second abnormality determination reference value, and determines presence or absence of the detection of the first abnormality or the second abnormality in the abnormality detection circuit depending on whether or not the current value indicated by the first digital signal is included within the first standard range or the second standard range.

7. The semiconductor device according to claim 6 ,
wherein the first abnormality has a higher priority than a priority of the second abnormality, and
the first fault current generated by the current generation circuit is larger than the second fault current.

8. An electronic control unit comprising a wiring substrate on which a semiconductor device formed by one package and a connector coupled to the semiconductor device are mounted,
wherein the semiconductor device includes:
a first semiconductor chip and a second semiconductor chip mounted on the one package; and
a load driving terminal,

the connector includes a load driving connector terminal coupled to the load driving terminal through a wiring on the wiring substrate and supplies power to a load,
the first semiconductor chip includes:
a power-supply transistor for supplying power to the load through the load driving terminal and the load driving connector terminal;
a driver circuit for driving the power-supply transistor;
a first terminal;
a current detecting resistor coupled to the first terminal so as to output a voltage in accordance with a flowing current to the first terminal;
an abnormality detection circuit for detecting an abnormality; and
a current generation circuit for generating a sense current on which a current flowing through the load driving terminal is reflected and a fault current indicating that the abnormality detection circuit has detected the abnormality so that the current generation circuit selects either the sense current or the fault current from the current generation circuit to flow through the current detecting resistor in accordance with presence or absence of detection of the abnormality, and

the second semiconductor chip includes:
a second terminal to be coupled to the first terminal;
a first analog-digital conversion circuit for converting an analog signal to be input to the second terminal into a first digital signal;
a s

Assignees

• Renesas Electronics Corp

Inventors

• Uemura Akira
• Soma Osamu

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/421

  Shapes or dispositions · CPC title

• H10W72/50

  Bond wires · CPC title