Transmission line design with routing-over-void compensation

Patent metadata

Field	Value
Publication number	US-10856407-B2
Application number	US-201816021618-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Jun 30, 2017
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the conductor can include a first part routed over a major surface of a first side of the reference plane structure and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of a second side of the reference plane structure and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory, and a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.

First claim

What is claimed is:

1. An apparatus comprising:
a reference plane structure;
a void between two edges of the reference plane structure;
a first signal conductor routed over a major surface of the reference plane structure and spanning the void;
wherein the first signal conductor includes:
a first part routed over the major surface of a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory;
a second part routed over the major surface of a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory;
a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void; and
wherein the reference plane structure includes:
a first reference plane including the first edge and configured to be at a first reference potential; and
a second reference plane including the second edge and configured to be at a second reference potential different from the first reference potential.

2. The apparatus of claim 1 , wherein a length of the third portion in the general direction of signal flow via the first signal conductor is larger than a distance across the void between the first edge and the second edge, the distance across the void measured at first edge where the first part approaches the first edge and at the second edge where the second part approaches the second edge.

3. The apparatus of claim 1 , wherein the third part forms a “U”-shape across the void.

4. The apparatus of claim 1 , wherein the third part forms an “S”-shape across the void.

5. The apparatus of claim 1 , including a second signal conductor routed over the major surface of the reference plane structure and spanning the void.

6. The apparatus of claim 5 , wherein the second signal conductor includes:
a first part routed over the major surface of a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory;
a second part routed over the major surface of a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory; and
a third portion connecting the first portion with the second portion and having a third trajectory departing from the first trajectory and the second trajectory, the third portion configured to span the void.

7. The apparatus of claim 6 , wherein a length of the third portion of the second signal conductor in the general direction of signal flow via the second signal conductor is larger than a distance across the void between the first edge and the second edge, the distance across the void measured at first edge where the first part of the second approaches the first edge and at the second edge where the second part approaches the second edge.

8. The apparatus of claim 6 , wherein the third part of the second signal conductor forms an “S”-shape across the void.

9. The apparatus of claim 8 , wherein the third part of the first signal conductor forms an “S”-shape across the void.

10. The apparatus of claim 9 , wherein the “S”-shape of the third part of the first signal conductor is nested with the “S”-shape of the third part of the second signal conductor.

11. The apparatus of claim 6 , wherein the third part of the second signal conductor forms a “U”-shape across the void; and
wherein the third part of the first signal conductor forms a “U”-shape across the void.

12. The apparatus of claim 11 , wherein an open end of the “U”-shape of the third part of the first signal conductor and an open end of the “U”-shape of the third part of the second signal conductor are adjacent to each other;
wherein a closed end of the “U”-shape of the third part of the first signal conductor and a closed end of the “U”-shape of the third part of the second signal conductor are distal from each other; and
wherein each closed end is opposite the corresponding open end of each of the first and second “U”-shaped signal conductor.

13. The apparatus of claim 11 , wherein an open end of the “U”-shape of the third part of the first signal conductor and an open end of the “U”-shape of the third part of the second signal conductor are distal from each other;
wherein a closed end of the “U”-shape of the third part of the first signal conductor and a closed end of the “U”-shape of the third part of the second signal conductor are adjacent each other; and
wherein each closed end is opposite the corresponding open end of each of the first and second “U”-shaped signal conductor.

14. The apparatus of claim 11 , wherein the “U”-shape of the third part of the first signal conductor is nested with the “U”-shape of the third part of the second signal conductor.

15. A system comprising:
a substrate including a reference plane structure;
a first integrated circuit chip mounted to the substrate;
a second integrated circuit chip; and
a signal conductor mounted to the substrate, the signal conductor configured to couple between the first chip and the second chip and to span a void in the reference plane structure, the signal conductor comprising:
a first part routed over the major surface of a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory;
a second part routed over the major surface of a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory in-line with the first trajectory;
a third portion connecting the first portion with the second portion and having a “U”-shape or an “S”-shape, the third portion configured to span the void; and
wherein the reference plane structure includes:
a first reference plane including the first edge and configured to be at a first reference potential; and
a second reference plane including the second edge and configured to be at a second reference potential different from the first reference potential.

16. The system of claim 15 , wherein the substrate is a printed circuit board.

17. The system of claim 15 , wherein the substrate is one of a plurality of substrates of an integrated circuit package.

18. The system of claim 17 , wherein the first integrated circuit is a processor; and
wherein the second integrated circuit is wireless communication controller.

19. The system of claim 18 , including an operator interface configured to control functions provided by the processor and the wireless controller and to display status indications of the processor and the wireless communication controller.

Assignees

• Intel Corp

Inventors

• Yong Khang Choong
• Cheah Bok Eng
• Kong Jackson Chung Peng
• Hall Stephen Harvey
• Lim Yun Rou

Classifications

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H05K1/0227

  Split or nearly split shielding or ground planes · CPC title