Miller Clamp driver with feedback bias control

Patent metadata

Field	Value
Publication number	US-10855263-B2
Application number	US-201916428345-A
Country	US
Kind code	B2
Filing date	May 31, 2019
Priority date	Aug 2, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

First claim

What is claimed is:

1. A circuit, comprising:
a voltage supply comprising an input terminal and an output terminal;
a driver circuit comprising:
a first input terminal coupled to the output terminal of the voltage supply;
a second input terminal;
an output terminal;
a first p-type field-effect transistor (FET) comprising:
a gate terminal;
a source terminal coupled to the output terminal of the voltage supply; and
a drain terminal coupled to the output terminal of the driver circuit; and

a first n-type FET comprising:
a gate terminal; a drain terminal coupled to the output terminal of the driver circuit and to the drain terminal of the first p-type FET; and a source terminal coupled to a ground terminal;

a Miller Clamp coupled between the output terminal of the driver circuit and
the ground terminal; and

a feedback bias circuit comprising:
an input terminal coupled to the output terminal of the driver circuit: and an output terminal coupled to the input terminal of the voltage supply.

2. The circuit of claim 1 , wherein the voltage supply comprises:
a current source comprising a first terminal and a second terminal;
a second n-type FET comprising:
a gate terminal coupled to the first terminal of the current source;
a drain terminal coupled to the second terminal of the current source; and
a source terminal;

a third n-type FET comprising:
a gate terminal coupled to the first terminal of the current source;
a drain terminal coupled to the first terminal of the current source; and
a source terminal;

a voltage source comprising:
a first terminal coupled to the source terminal of the third n-type FET; and
a second terminal coupled to the ground terminal;

a resistor coupled between the source terminal of the second n-type FET and the ground terminal; and
a capacitor coupled between the source terminal of the second n-type FET and the ground terminal.

3. The circuit of claim 1 , wherein the driver circuit further comprises:
a first driver comprising:
an input terminal coupled to the second input terminal of the driver circuit;
an output terminal; and
a supply terminal coupled to the output terminal of the voltage supply; and

a second driver comprising:
an input terminal;
an output terminal; and
a supply terminal coupled to the output terminal of the voltage supply.

4. The circuit of claim 1 , wherein the feedback bias circuit comprises:
a second p-type FET comprises:
a gate terminal coupled to the driver circuit; a drain terminal coupled to the output terminal of the driver circuit; and a source terminal;

a fourth n-type FET comprising;
a gate terminal coupled to the input terminal of the voltage supply;
a source terminal coupled to the source terminal of the second p-type FET; and
a drain terminal;

a third p-type FET comprising:
a gate terminal coupled to the drain terminal of the fourth n-type FET; a drain terminal coupled to the drain terminal of the fourth n-type FET; and a source terminal; and

a fourth p-type FET comprising:
a gate terminal coupled to the drain terminal of the fourth n-type FET; a drain terminal coupled to the input terminal of the voltage supply; and

a source terminal coupled to the source terminal of the third p-type FET.

5. The circuit of claim 1 , wherein the voltage supply is configured to:
generate a reference voltage;
modulate the reference voltage based on an output of the feedback bias circuit to generate an internal supply signal; and
drive the driver circuit with the internal supply signal.

6. The circuit of claim 5 , wherein the circuit does not comprise a low dropout regulator (LDO).

7. A circuit, comprising:
a voltage supply configured to generate an internal supply signal according to a reference voltage and a feedback signal, the voltage supply comprising:
a current source comprising a first terminal and a second terminal;
a first n-type field-effect transistor (FET) comprising:
a gate terminal coupled to the first terminal of the current source;
a drain terminal coupled to the second terminal of the current source, and
a source terminal;

a second n-type FET comprising:
a gate terminal coupled to the first terminal of the current source;
a drain terminal coupled to the first terminal of the current source; and
a source terminal;

a voltage source comprising:
a first terminal coupled to the source terminal of the second n-type FET; and
a second terminal coupled to a ground terminal;

a resistor coupled between the source terminal of the first n-type FET and the ground terminal; and
a capacitor coupled between the source terminal of the first n-type FET and the ground terminal;

a driver circuit comprising:
a first input terminal coupled to the source terminal of the first n-type FET; and
an output terminal, wherein the driver circuit is configured to drive the output terminal of the driver circuit with the internal supply signal in accordance with a control signal; and

a feedback bias circuit configured to detect an output current flowing to the output terminal of the driver circuit and generate the feedback signal according to the output current, the feedback bias circuit comprising:
an input terminal coupled to the output terminal of the driver circuit; and an output terminal coupled to the first terminal of the current source.

8. The circuit of claim 7 , wherein the driver circuit comprises:
a first driver comprising:
an input terminal configured to receive the control signal;
an output terminal; and
a supply terminal coupled to the source terminal of the first n-type FET;

a second driver comprising:
an input terminal configured to receive the control signal;
an output terminal; and
a supply terminal coupled to the source terminal of the first n-type FET;

a first p-type FET comprising:
a gate terminal coupled to the output terminal of the first driver;
a source terminal coupled to the source terminal of the first n-type FET; and
a drain terminal coupled to the output terminal of the driver circuit; and

a third n-type FET comprising:
a gate terminal coupled to the output terminal of the second driver,
a drain terminal coupled to the output terminal of the driver circuit; and
a source terminal coupled to the ground terminal.

9. The circuit of claim 8 , wherein the feedback bias circuit comprises:
a second p-type FET configured to detect the output current, the second p-type FET comprising:
a gate terminal coupled to the output terminal of the first driver;
a drain terminal coupled to the output terminal of the driver circuit; and
a source terminal;

a fourth n-type FET comprising:
a gate terminal coupled to the first terminal of the current source;
a source terminal coupled to the source terminal of the second p-type FET; and
a drain terminal;

a third p-type FET comprising:
a gate terminal coupled to the drain terminal of the fourth n-type FET;
a drain terminal coupled to the drain terminal of the fourth n-type FET; and
a source terminal coupled to the second terminal of the current source; and

a fourth p-type FET comprising:
a gate terminal coupled to the drain terminal of the fourth n-type FET;
a drain terminal coupled to the first terminal of the current source; and
a source terminal coupled to the second terminal of the current source.

10. The circuit of claim 7 , further comprising a Miller Clamp coupled between the output terminal of the driver circuit and the ground terminal.

11. The circuit of claim 7 , wherein the voltage supply does not comprise a low dropout regulator (LDO).

12. A system, compri

Assignees

• Texas Instruments Inc

Inventors

• Ju Shuing
• Tan Wenxiao
• Rao Arun

Classifications

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H03K4/48 Primary

  using as active elements semiconductor devices (H03K4/787 - H03K4/84 take precedence) · CPC title