Semiconductor circuit including a DC-DC converter and a voltage regulator

Patent metadata

Field	Value
Publication number	US-10855185-B2
Application number	US-201916394611-A
Country	US
Kind code	B2
Filing date	Apr 25, 2019
Priority date	Sep 10, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A semiconductor circuit includes a reference voltage generating circuit which generates a first reference voltage; a voltage control circuit which receives the first reference voltage from the reference voltage generating circuit to output a second reference voltage; a DC-DC conversion circuit which executes DC-DC conversion on the basis of the second reference voltage which is output from the voltage control circuit, and provides an output thereof to a first node; and a voltage regulator which executes voltage regulating on the basis of the first reference voltage which is output from the reference voltage generating circuit, and a voltage of the first node, and provides an output thereof to a second node.

First claim

What is claimed is:

1. A semiconductor circuit comprising:
a voltage control circuit configured to generate a second reference voltage by adding, to a first reference voltage, a dropout voltage corresponding to a difference between an input voltage and an output voltage;
a DC-DC conversion circuit configured to perform DC-DC conversion based on the second reference voltage to generate the input voltage such that the dropout voltage corresponding to the difference between the input voltage and the output voltage is constantly maintained at a difference between the second reference voltage and the first reference voltage, and to provide the input voltage to a first node; and
a voltage regulator configured to generate the output voltage by regulating the input voltage based on the first reference voltage and the input voltage; and
a reference voltage generating circuit configured to generate a first reference voltage, and to separately provide the first reference voltage to both the voltage control circuit that generates the second reference voltage used to generate the input voltage and to the voltage regulator that regulates the input voltage to generate the output voltage.

2. The semiconductor circuit of claim 1 , wherein the semiconductor circuit is configured to maintain the dropout voltage at a constant voltage level during operation of the semiconductor circuit irrespective of variations in the input voltage generated by the DC-DC-conversion circuit due to fluctuations in the output voltage generated by the voltage regulator.

3. The semiconductor circuit of claim 1 , wherein the DC-DC conversion circuit comprises:
a first comparator including a non-inverting terminal and an inverting terminal, the non-inverting terminal configured to receive the second reference voltage and the inverting terminal configured to receive the input voltage from the first node,
a control circuit configured to receive an output signal of the first comparator, and to generate a first control signal and a second control signal based on the output signal,
a first transistor having a gate configured to receive the first control signal, the first transistor configured to selectively provide a power supply voltage to the first node based on the first control signal, and
a second transistor having a gate configured to receive the second control signal, the second transistor configured to selectively provide a ground voltage to the first node based on the second control signal.

4. The semiconductor circuit of claim 3 , wherein
the first transistor is a P type transistor,
the second transistor is an N-type transistor, and
a drain of the first transistor is connected to a drain of the second transistor.

5. The semiconductor circuit of claim 1 , wherein the voltage regulator comprises:
a second comparator including an inverting terminal and a non-inverting terminal, the inverting terminal configured to receive the first reference voltage and the non-inverting terminal configured to receive the output voltage of the second node, and
a third transistor having a gate configured to receive an output signal of the second comparator, the third transistor configured to selectively provide a voltage of the first node to the second node based on the output signal.

6. The semiconductor circuit of claim 5 , wherein the third transistor is a P type transistor, the third transistor including a source and a drain, the source of the third transistor being connected to the first node such that the source of the third transistor receives the input voltage, and the drain of the third transistor being connected to the second node such that the drain of the third transistor receives the output voltage.

7. The semiconductor circuit of claim 1 , wherein the voltage control circuit comprises:
a level shift circuit.

8. The semiconductor circuit of claim 1 , wherein the voltage control circuit is disposed inside the DC-DC conversion circuit.

9. The semiconductor circuit of claim 1 , wherein the voltage control circuit is disposed outside the DC-DC conversion circuit such that the voltage control circuit is configured to provide the second reference voltage to the DC-DC conversion circuit through a third node.

10. The semiconductor circuit of claim 1 , wherein the voltage regulator is configured to provide a drive voltage to a device under test (DUT) through the second node, and the voltage regulator comprises:
a third comparator including a non-inverting terminal and an inverting terminal, the non-inverted terminal configured to receive a first input from the device under test and the inverting terminal configured to receive a second input from the device under test,
a second comparator including an inverting terminal and a non-inverting terminal, the inverting terminal configured to receive the first reference voltage and the non-inverting terminal configured to receive an output of the third comparator, and
a third transistor having a gate configured to receive an output signal of the second comparator, the third transistor configured to selectively provide the input voltage of the first node to the second node based on the output signal.

11. The semiconductor circuit of claim 10 , wherein the third transistor is a P type transistor, and the third transistor includes a source and a drain, the source of the third transistor being connected to the first node such that the source of the third transistor receives the input voltage, and the drain of the third transistor being connected to the second node such that the drain of the third transistor receives the output voltage.

12. The semiconductor circuit of claim 1 , further comprising:
a voltage adjust circuit configured to transmit a command signal to the voltage control circuit, wherein
the voltage control circuit is configured to adjust a level of the second reference voltage based on the command signal.

13. A semiconductor circuit comprising:
a reference voltage generating circuit configured to generate a first reference voltage;
a DC-DC conversion circuit configured to perform DC-DC conversion based on a second reference voltage to generate an input voltage, and to provide the input voltage to a first node, the second reference voltage having a voltage level different from the first reference voltage; and
a voltage regulator configured to generate an output voltage by regulating the input voltage based on the first reference voltage and the input voltage such that the reference voltage generating circuit separately provides the first reference voltage to both the DC-DC conversion circuit that generates the input voltage and to the voltage regulator that regulates the input voltage to generate the output voltage, and to provide the output voltage to a second node, wherein
the semiconductor circuit is configured to maintain a constant difference between the input voltage output by the DC-DC conversion circuit and the output voltage output by the voltage regulator by varying the input voltage based on a difference between the second reference voltage and the first reference voltage such that the constant difference corresponds to the difference between the second reference voltage and the first reference voltage irrespective of variations in the input voltage due to fluctuations in the output voltage.

14. The semiconductor circuit of claim 13 , wherein the DC-DC conversion circuit comprises:
a first comparator including a non-inverting terminal and an inverting terminal, the non-inverting terminal configured to receive the second reference voltage and the inverting terminal configured to receive the input voltage f

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Ki Jae
• Yoo Jong Woon

Classifications

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• H02M3/157

  with digital control · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title