Semiconductor device

US10854589B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10854589-B2
Application numberUS-201916507240-A
CountryUS
Kind codeB2
Filing dateJul 10, 2019
Priority dateJan 18, 2017
Publication dateDec 1, 2020
Grant dateDec 1, 2020

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a first semiconductor module and a second semiconductor module. The first semiconductor module configures an upper arm, and includes first semiconductor elements connected in parallel to each other, a sealing resin body, and a positive electrode terminal. The second semiconductor module configures a lower arm, and includes second semiconductor elements connected in parallel to each other, a sealing resin body, and a negative electrode terminal. The first and second semiconductor modules are aligned in an alignment direction. At least one of the first and second semiconductor modules has a relay terminal for electrically relaying electrodes on a low potential side of the first semiconductor elements and electrodes on a high potential side of the second semiconductor elements.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device which configures upper and lower arms, and is to be stacked on a cooler in a stacking direction so as to be cooled, the semiconductor device comprising: a first semiconductor module configuring the upper arm, the first semiconductor module including a plurality of first semiconductor elements connected in parallel to each other, a first resin body integrally sealing the plurality of first semiconductor elements, and a positive electrode terminal electrically connected to electrodes of the first semiconductor elements on a high potential side and protruding from the first resin body; and a second semiconductor module configuring the lower arm, the second semiconductor module including a plurality of second semiconductor elements connected in parallel to each other, a second resin body integrally sealing the plurality of first semiconductor elements, and a negative electrode terminal electrically connected to electrodes of the second semiconductor elements on a low potential side and protruding from the second resin body, and the second semiconductor module and the first semiconductor module being aligned in an alignment direction orthogonal to the stacking direction, wherein: the negative electrode terminal protrudes from one of side surfaces of the second resin body, on a same side as that of a side surface of the first resin body from which the positive electrode terminal protrudes, the first semiconductor module includes a first relay terminal which is electrically connected to electrodes of the first semiconductor elements on a low potential side, and protrudes from the first resin body, the second semiconductor module includes a second relay terminal which is electrically connected to electrodes of the second semiconductor elements on a high potential side, and protrudes from the second resin body, a portion of the first relay terminal protruding from the first resin body is connected to a portion of the second relay terminal protruding from the second resin body so as to provide a relay terminal that electrically relays the electrodes of the first semiconductor elements on the low potential side and the electrodes of the second semiconductor elements on the high potential side, the first relay terminal and the second relay terminal protrude from surfaces of the first resin body and the second resin body, respectively, the surfaces facing each other, the portion of the first relay terminal, which protrudes from the first resin body and the portion of the second relay terminal, which protrudes from the second resin body, are disposed in a facing region between the first resin body and the second resin body, the first semiconductor elements and the second semiconductor elements are disposed such that the electrodes of the first semiconductor elements on the high potential side and the electrodes of the second semiconductor elements on the high potential side are disposed on a same side in the stacking direction, the first semiconductor module includes a first dummy terminal that is electrically connected to the electrodes of the first semiconductor elements on the high potential side, and protrudes from a surface of the first resin body opposite to the first relay terminal, and the second semiconductor module includes a second dummy terminal that is electrically connected to the electrodes of the second semiconductor elements on the low potential side, and protrudes from a surface of the second resin body opposite to the second relay terminal. 2. The semiconductor device according to claim 1 , wherein: the first semiconductor module includes a low potential side terminal that is electrically connected to the electrodes of the first semiconductor elements on the low potential side, and protrudes from the same side surface of the first resin body from which the positive electrode terminal protrudes, the second semiconductor module includes a high potential side terminal that is electrically connected to the electrodes of the second semiconductor elements on the high potential side, and protrudes from the same side surface of the second resin body from which the negative electrode terminal protrudes, and one of the low potential side terminal and the high potential side terminal is provided as an output terminal, and the other of the low potential side terminal and the high potential side terminal is provided as a dummy terminal. 3. The semiconductor device according to claim 1 , wherein: the positive electrode terminal protrudes from a position closer to the second semiconductor module than a center of the first semiconductor module in the alignment direction of the first semiconductor module and the second semiconductor module, and the negative electrode terminal protrudes from a position closer to the first semiconductor module than a center of the second semiconductor module in the alignment direction. 4. The semiconductor device according to claim 1 , wherein the negative electrode terminal is disposed adjacent to the positive electrode terminal in the alignment direction of the first semiconductor module and the second semiconductor module. 5. The semiconductor device according to claim 1 , wherein the portion of the first relay terminal protruding from the first resin body and the portion of the second relay terminal protruding from the second resin body are located at a same position in a direction orthogonal to both of the alignment direction of the first semiconductor module and the second semiconductor module and the stacking direction. 6. The semiconductor device according to claim 1 , further comprising a third resin body that integrally holds the first semiconductor module and the second semiconductor module.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • characterised by arrangements for sealing or adhesion · CPC title

  • by flowing liquids, e.g. forced water cooling · CPC title

  • characterised by their shape, e.g. having conical or cylindrical projections · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

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Frequently asked questions

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What does patent US10854589B2 cover?
A semiconductor device includes a first semiconductor module and a second semiconductor module. The first semiconductor module configures an upper arm, and includes first semiconductor elements connected in parallel to each other, a sealing resin body, and a positive electrode terminal. The second semiconductor module configures a lower arm, and includes second semiconductor elements connected …
Who is the assignee on this patent?
Denso Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).