Die stack assembly using an edge separation structure for connectivity through a die of the stack

Patent metadata

Field	Value
Publication number	US-10854581-B2
Application number	US-202016869907-A
Country	US
Kind code	B2
Filing date	May 8, 2020
Priority date	Feb 29, 2016
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.

First claim

What is claimed is:

1. An assembly comprising:
a first power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface, wherein a peripheral edge separation structure extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the first power semiconductor device die, wherein the peripheral edge separation structure comprises an amount of P type semiconductor material disposed in a trench, and a P type semiconductor region that is doped at least in part with aluminum, and wherein a metal feature covers and makes electrical contact with the peripheral edge separation structure at the first substantially planar semiconductor surface of the first power semiconductor device die; and
a second power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface, wherein a peripheral edge separation diffusion region extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the second power semiconductor device die, wherein the peripheral edge separation diffusion region is a P type semiconductor region that is doped at least in part with aluminum, and wherein the second power semiconductor device die is bonded to the first power semiconductor device die such that the metal feature is electrically coupled within the assembly through the peripheral edge separation structure of the first power semiconductor device die to the peripheral edge separation diffusion region of the second power semiconductor device die;
wherein an uncovered portion of the metal feature is not covered with any passivation layer of the first die, wherein the uncovered portion of the metal feature extends at least one hundred microns in a direction perpendicular to the side edge of the first power semiconductor device die, and wherein the uncovered metal feature extends at least one hundred microns in a direction parallel to the side edge of the first power semiconductor device die; and
wherein the metal feature is a four-sided metal ring that extends along four side edges of the first die.

2. The assembly of claim 1 , further comprising:
a substrate comprising a rigid insulative body layer, a first patterned metal feature disposed on the rigid insulative body layer, and a second patterned metal feature disposed on the rigid insulative body layer, wherein the second power semiconductor device die is bonded to the substrate such that a first metal electrode of the second power semiconductor device die is bonded to the first patterned metal feature of the substrate and such that the second metal electrode of the second power semiconductor device die is bonded to the second patterned metal feature of the substrate.

3. The assembly of claim 1 , wherein the first power semiconductor device die has a control electrode disposed on the first substantially planar semiconductor surface of the first power semiconductor device die, and wherein the second power semiconductor device die has a control electrode disposed on the first substantially planar semiconductor surface of the second power semiconductor device die.

4. The assembly of claim 1 , further comprising:
a substrate having an insulative body layer and a patterned metal feature, wherein the second power semiconductor device die is bonded to the substrate such that a metal electrode of the second power semiconductor device die is bonded to the patterned metal feature of the substrate, wherein at least a part of the metal electrode of the second power semiconductor device die is in physical contact with the peripheral edge separation diffusion region of the second power semiconductor device die.

5. The assembly of claim 1 , further comprising:
a metal member; and
an interface member having an insulative body and a patterned metal feature, wherein the interface member is disposed between the second semiconductor device die and metal member, wherein the interface member provides an electrical connection between the metal member and a metal electrode of the second power semiconductor device die, wherein the second power semiconductor device die has a passivation layer of a thickness, wherein the interface member has thickness that is greater than the thickness of the passivation layer, wherein the second power semiconductor device die has a thickness between the first and second substantially planar semiconductor surfaces of the second power semiconductor device die, and wherein the thickness of the interface member is smaller than a thickness of the second power semiconductor device die.

6. The assembly of claim 1 , wherein the first power semiconductor device die further comprises a metal layer disposed on the second substantially planar semiconductor surface of the first power semiconductor device die, wherein the second power semiconductor device die further comprises a metal layer disposed on the second substantially planar semiconductor surface of the second power semiconductor device die, and wherein the metal layer of the first power semiconductor device die is bonded to the metal layer of the second power semiconductor device die.

7. The assembly of claim 6 , further comprising:
a layer comprising silver, wherein the layer comprising silver bonds the metal layer disposed on the second substantially planar semiconductor surface of the first power semiconductor device die to the metal layer disposed on the second substantially planar semiconductor surface of the second power semiconductor device die.

8. An assembly comprising:
a first power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface, wherein a peripheral edge separation structure extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the first power semiconductor device die, wherein the peripheral edge separation structure comprises an amount of P type semiconductor material disposed in a trench, and a P type semiconductor region that is doped at least in part with aluminum, and wherein a metal feature covers and makes electrical contact with the peripheral edge separation structure at the first substantially planar semiconductor surface of the first power semiconductor device die; and
a second power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface, wherein a peripheral edge separation diffusion region extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the second power semiconductor device die, wherein the peripheral edge separation diffusion region is a P type semiconductor region that is doped at least in part with aluminum, and wherein the second power semiconductor device die is bonded to the first power semiconductor device die such that the metal feature is electrically coupled within the assembly through the peripheral edge separation structure of the first power semiconductor device die to the peripheral edge separation diffusion region of the second power semiconductor device die;
wherein an uncovered portion of the metal feature is not covered with any passivation layer of the first die, wherein the uncovered portion of the metal feature extends at least one hundred microns in a direction perpendicular to the side edge of the first power semiconductor device die, and wherein the uncovered metal feature extend

Assignees

• Littelfuse Inc

Inventors

• Wisotzki Elmar
• Ettingshausen Frank

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title