Power semiconductor device and power module

US10854537B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10854537-B2
Application numberUS-201816124932-A
CountryUS
Kind codeB2
Filing dateSep 7, 2018
Priority dateApr 11, 2018
Publication dateDec 1, 2020
Grant dateDec 1, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a small-sized power semiconductor device in which interference between power modules adjacently disposed is prevented and the areas of the gaps occurring between the power modules are reduced. In a power semiconductor device formed by adjacently disposing power modules in an arc shape on a heat sink, each of which power modules is obtained by sealing, with a mold resin, a switchable power semiconductor chip, a lead frame in which potential leads and signal terminals connected to the power semiconductor chip are formed, and a metallic inner lead electrically connecting an upper surface electrode of the power semiconductor chip and the lead frame, any one of the adjacent power modules is formed in a pentagonal shape having, at a portion adjacent to the other power module, an oblique side 10a obtained by cutting out one corner of a quadrangle.

First claim

Opening claim text (preview).

What is claimed is: 1. A power semiconductor device formed by adjacently disposing a plurality of power modules in along an arc on a heat sink, each power module being obtained by sealing, with a mold resin, a switchable power semiconductor chip, a lead frame in which a potential lead and a signal terminal connected to the power semiconductor chip are formed, and a metallic inner lead electrically connecting an upper surface electrode of the power semiconductor chip and the lead frame, wherein any one of the adjacent power modules is formed in a pentagonal shape having, at a portion adjacent to the other power module, an oblique side obtained by cutting out one corner of a quadrangle, and the signal terminal is disposed at a side corresponding to a radially outer peripheral side of each of the power modules with respect to a radius of the arc. 2. The power semiconductor device according to claim 1 , wherein the potential lead is disposed at a side corresponding to an inner peripheral side of each of the power modules. 3. The power semiconductor device according to claim 2 , wherein each of the power modules includes a bridge circuit for one phase, and the n power modules are disposed in an arc shape on a shared heat sink to form an n-phase bridge circuit. 4. The power semiconductor device according to claim 3 , wherein the mold resin is a transfer mold resin, and the power semiconductor chip, the lead frame, and the inner lead are over-molded therewith. 5. The power semiconductor device according to claim 2 , wherein the mold resin is a transfer mold resin, and the power semiconductor chip, the lead frame, and the inner lead are over-molded therewith. 6. The power semiconductor device according to claim 1 , wherein each of the power modules includes a bridge circuit for one phase, and the n power modules are disposed in an arc shape on a shared heat sink to form an n-phase bridge circuit. 7. The power semiconductor device according to claim 6 , wherein the mold resin is a transfer mold resin, and the power semiconductor chip, the lead frame, and the inner lead are over-molded therewith. 8. The power semiconductor device according to claim 1 , wherein the mold resin is a transfer mold resin, and the power semiconductor chip, the lead frame, and the inner lead are over-molded therewith. 9. A power module comprising: a switchable power semiconductor chip; a lead frame in which a potential lead and a signal terminal connected to the power semiconductor chip are formed; a metallic inner lead electrically connecting an upper surface electrode of the power semiconductor chip and the lead frame; a conductive joining member joining at least the lead frame and the inner lead together; and a mold resin covering the power semiconductor chip, the lead frame, and the inner lead, wherein an outer shape of the mold resin is formed as a pentagonal shape having an oblique side obtained by cutting out one corner of a quadrangle, wherein the signal terminal is disposed at a long side opposing a short side connected to the oblique side. 10. The power module according to claim 9 , wherein the potential lead is disposed at the short side connected to the oblique side. 11. The power module according to claim 9 , wherein the mold resin is a transfer mold resin, and the power semiconductor chip, the lead frame, and the inner lead are over-molded therewith.

Assignees

Inventors

Classifications

  • characterised by changes in properties of the strap connectors during connecting · CPC title

  • Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • Multiple chips on leadframes · CPC title

  • Package configurations · CPC title

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What does patent US10854537B2 cover?
Provided is a small-sized power semiconductor device in which interference between power modules adjacently disposed is prevented and the areas of the gaps occurring between the power modules are reduced. In a power semiconductor device formed by adjacently disposing power modules in an arc shape on a heat sink, each of which power modules is obtained by sealing, with a mold resin, a switchable…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/481. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).