Display panel and display device including the same

Patent metadata

Field	Value
Publication number	US-10854124-B2
Application number	US-201916459386-A
Country	US
Kind code	B2
Filing date	Jul 1, 2019
Priority date	Mar 29, 2019
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A display panel has a display area and a non-display area surrounding the display area. The display area has a first side and a second side opposite to the first side, and includes: a hollow area having first and second edges; and first to fourth display areas. The display panel includes: a driving chip arranged in the non-display area close to the first side; first data lines arranged in the first display area; second data lines arranged in the second display area; third data lines arranged in the third display area; and fourth data lines arranged in the fourth display area. The first edge is close to the driving chip and the second edge is away from the driving chip, and each second signal line is connected to at least two third data lines through a signal switching circuit.

First claim

What is claimed is:

1. A display panel, having a display area and a non-display area surrounding the display area, wherein the display area has a first side and a second side opposite to the first side, and the display area comprises:
a hollow area having a first edge and a second edge;
a first display area extending from the first side of the display area to the second side of the display area;
a second display area extending from the first side of the display area to an extension line of the second edge of the hollow area;
a third display area extending from the extension line of the second edge and the second edge of the hollow area to the second side of the display area; and
a fourth display area extending from the first side of the display area to the first edge of the hollow area,
wherein the display panel comprises:
a driving chip arranged in the non-display area close to the first side of the display area;
first data lines arranged in the first display area, wherein each of the first data lines extends from the first side of the display area to the second side of the display area;
second data lines arranged in the second display area;
third data lines arranged in the third display area; and
fourth data lines arranged in the fourth display area,
wherein the first edge of the hollow area is close to the driving chip and the second edge of the hollow area is away from the driving chip, and wherein each of the second data lines is electrically connected to n third data lines of the third data lines through a set of signal switching circuits in such a manner that a signal on said second data line is transmitted to n third data lines in a time division manner via the set of signal switching circuits, wherein n is an integer equal to or larger than 2 and no larger than a total number of the third data lines.

2. The display panel according to claim 1 , further comprising compensation capacitors connected to the fourth data lines, each of the compensation capacitors has a capacitance of C1, wherein a difference between a parasitic capacitance of each of the first data lines and a parasitic capacitance of each of the second data lines is C2, and 0.8*C 2 ≤C1≤1.2*C 2 .

3. The display panel according to claim 2 , wherein the compensation capacitors are arranged at the first edge of the hollow area close to the fourth display area.

4. The display panel according to claim 1 , wherein the set of signal switching circuits comprise n transistors and n control signal lines, each of the n transistors has a first terminal connected to one of the second data lines, a second terminal connected to one of the n third data lines, and a control terminal connected to one of the n control signal lines.

5. The display panel according to claim 4 , wherein one of the second data lines corresponds to a set of signal switching circuits, and the signal switching circuits are arranged at the second edge of the hollow area close to the third display area, or
one of the second data lines corresponds to a set of signal switching circuits, and the signal switching circuits are arranged between the n third data lines connected to said second data line.

6. The display panel according to claim 5 , further comprising:
a plurality of pixels, each having an anode, a cathode, and a light-emitting material layer arranged between the anode and the cathode; and
a plurality of pixel driving circuits, each of the plurality of pixel driving circuits corresponding to one of the plurality of pixels and being connected to the anode of the one pixel;
each of the plurality of pixel driving circuits located in the third display area has a size smaller than a size of each of the plurality of pixel driving circuits located in the first display area;
the anode covers at least a portion of the signal switching circuit.

7. The display panel according to claim 4 ,
wherein the display area has a third side adjacent to the first side and the second side, and a fourth side opposite to the third side;
the hollow area is arranged at the third side of the display area and forms a notch area;
each of the n control signal lines extends towards the third side of the display area, and extends from the non-display area close to the third side of the display area to the driving chip.

8. The display panel according to claim 4 ,
wherein the display area has a third side adjacent to the first side and the second side, and a fourth side opposite to the third side;
the hollow area is arranged in a middle area of the display area and forms a non-display hole;
the n control signal lines comprise a first control signal line extending towards the third side, and a second control signal line extending towards the fourth side, the first control signal line extends from the non-display area close to the third side to the driving chip, and the second control signal line extends from the non-display area close to the fourth side to the driving chip.

9. The display panel according to claim 4 ,
wherein the set of signal switching circuits comprises a first transistor and a second transistor;
wherein a first electrode of the first transistor and a first electrode of the second transistor are both connected to one of the second data lines;
wherein the first transistor has a second electrode connected to one third data line in a first group of third data lines, and the second transistor has a second electrode connected to one third data line in a second group of third data lines that is adjacent to the one third data line in the first group of third data lines;
wherein the first transistor has a gate connected to a first control signal line, and the second transistor has a gate connected to a second control signal line;
wherein the set of signal switching circuits comprises a linear active layer extending in a first direction, the active layer having a first end and a second end connected to the one third data line in the first group of third data lines and the one third data line in the second group of third data lines respectively, and a middle area of the active layer is connected to one of the second data lines, and
wherein each one of the first control signal line and the second control signal line comprises a gate portion extending in a second direction intersecting the first direction and a body portion, the body portion does not overlap the active layer, and the gate portion overlaps the active layer.

10. The display panel according to claim 1 , further comprising:
scan lines extending in a first direction and arranged in a second direction; and
data lines extending in the second direction and arranged in the first direction,
wherein the display area has a third side adjacent to the first side and the second side, and a fourth side opposite to the third side; the hollow area is arranged at the third side and forms a notch area; and the notch area has a third edge adjacent to both the first edge and the second edge;
wherein in the first direction, the first display area is adjacent to the fourth side of the display area, the second display area is arranged between the first display area and the third edge of the notch area, the third display area is arranged between the first display area and the third side of the display area, and the fourth display area is arranged between the third edge of the notch area and the third side of the display area;
the first display area comprises a first portion aligned with the third display area in the first direction, and a second portion aligned with the second display area in the first direction;
wherein in a first period, the first portion of the first display area and the third display area are simultaneously driven

Assignees

• Shanghai Tianma Am Oled Co Ltd

Inventors

• Yang Yang
• Tang Shuo
• Lv Bojia
• Kong Xiangzi
• Li Jun

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title