Coarse compute shading

Patent metadata

Field	Value
Publication number	US-10853989-B2
Application number	US-201816142692-A
Country	US
Kind code	B2
Filing date	Sep 26, 2018
Priority date	Sep 26, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A method, comprising:
maintaining a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse rate version of a course compute shader executed in a graphics processing device;
receiving a request message to dispatch coarse compute shader work of the coarse compute shader, the request message comprising a requested level of coarseness and a thread identifier;
storing the request message in a FIFO queue structure of the plurality of FIFO queue structures having the coarse rate version corresponding to the requested level of coarseness associated with the request message;
generating a message with instructions to dispatch a compute shader thread having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the coarse compute shader work with a fully populated single instruction multiple data (SIMD) thread;
forwarding the message to a thread dispatcher; and
releasing data in the FIFO queue structure with the message to the thread dispatcher.

2. The method of claim 1 , further comprising:
receiving payload data with the request message; and
storing the payload data in the computer readable memory.

3. The method of claim 1 , further comprising:
generating a message with instructions to dispatch a compute shader thread using a shader code that corresponds to the level of coarseness of the FIFO queue structure in response to a determination that the FIFO queue structure comprises a number of request messages sufficient to dispatch the course compute shader work with a fully populated single instruction multiple data (SIMD) thread; and
forwarding the message to a thread dispatcher.

4. The method of claim 3 , further comprising:
releasing data in the FIFO queue structure with the message to the thread dispatcher.

5. A non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising:
maintaining a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse rate version of a course compute shader executed in a graphics processing device;
receiving a request message to dispatch coarse compute shader work of the coarse compute shader, the request message comprising a requested level of coarseness and a thread identifier;
storing the request message in a FIFO queue structure of the plurality of FIFO queue structures having the coarse rate version corresponding to the requested level of coarseness associated with the request message;
generating a message with instructions to dispatch a compute shader thread having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the coarse compute shader work with a fully populated single instruction multiple data (SIMD) thread;
forwarding the message to a thread dispatcher; and
releasing data in the FIFO queue structure with the message to the thread dispatcher.

6. The non-transitory machine readable medium of claim 5 , the operations additionally comprising:
receiving payload data with the request message; and
storing the payload data in the computer readable memory.

7. The non-transitory machine readable medium of claim 5 , the operations additionally comprising:
generating a message with instructions to dispatch a compute shader thread having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the course compute shader work with a fully populated single instruction multiple data (SIMD) thread; and
forwarding the message to a thread dispatcher.

8. An apparatus, comprising:
a processor to:
maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse rate version of a course compute shader executed in a graphics processing device;
receive a request message to dispatch coarse compute shader work of the coarse compute shader, the request message comprising a requested level of coarseness and a thread identifier; and
store the request message in a FIFO queue structure of the plurality of FIFO queue structures having the coarse rate version corresponding to the requested level of coarseness associated with the request message;
generate a message with instructions to dispatch a compute shader thread having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the coarse compute shader work with a fully populated single instruction multiple data (SIMD) thread;
forward the message to a thread dispatcher; and
release data in the FIFO queue structure with the message to the thread dispatcher; and
a memory communicatively coupled to the processor.

9. The apparatus of claim 8 , the processor to:
receive payload data with the request message; and
store the payload data in the computer readable memory.

10. The apparatus of claim 8 , the processor to:
generate a message with instructions to dispatch a compute having a coarseness level corresponding to the level of coarseness of the FIFO queue structure in response to a determination that a watchdog timer expired before the FIFO queue structure comprises a number of request messages sufficient to dispatch the course compute shader work with a fully populated single instruction multiple data (SIMD) thread; and
forward the message to a thread dispatcher.

11. The apparatus of claim 10 , the processor to:
release data in the FIFO queue structure with the message to the thread dispatcher.

Assignees

• Intel Corp

Inventors

• Gierach John

Classifications

• G06T15/80

  Shading · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06T15/50

  Lighting effects · CPC title