Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
US10853549B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10853549-B2 |
| Application number | US-201715659548-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 25, 2017 |
| Priority date | Jul 26, 2016 |
| Publication date | Dec 1, 2020 |
| Grant date | Dec 1, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A piezoelectric open-circuit output voltage profile simulator including a capacitor; at least first, second and third switches; and a controller for controlling the first, second and third switches.
Opening claim text (preview).
What is claimed is: 1. An open-circuit output voltage profile simulator comprising: a piezoelectric power source configured to provide an open-circuit output voltage; a first capacitor; at least first, second and third switches; a controller for controlling the first, second and third switches, a second capacitor couplable in parallel to the first capacitor under control of the second switch; a first resistor coupled in series between the first and second switches; and a second resistor coupled in series between the second and third switches; wherein the first capacitor is coupled to the power source through the first switch to control a charge profile of the simulator, and wherein the second and third switch are coupled to the first capacitor to control a discharge profile of the simulator. 2. The simulator of claim 1 , wherein the third switch controls coupling of the second resistor in parallel with the second capacitor. 3. The simulator of claim 2 , wherein the power source, the first and second capacitors, the first and second resistors, and the least first, second and third switches comprise a first open-circuit voltage profile generator, the simulator comprising at least one second open-circuit voltage profile generator couplable in parallel with the first open-circuit voltage profile generator under control of the controller. 4. The simulator of claim 1 , wherein the first resistor comprises a plurality of first resistors selectively couplable in parallel at least in pairs under control of the controller. 5. The simulator of claim 1 , wherein the second resistor comprises a plurality of second resistors selectively couplable in parallel at least in pairs under control of the controller. 6. The simulator of claim 1 , wherein at least one of the first and second resistors comprise a plurality of resistors selectively couplable in parallel at least in pairs under control of the controller. 7. The simulator of claim 6 , wherein the power source, the first and second capacitors, the first and second resistors, and the least first, second and third switches comprise a first open-circuit voltage profile generator, the simulator comprising at least one second open-circuit voltage profile generator couplable in parallel with the first open-circuit voltage profile generator under control of the controller. 8. The simulator of claim 1 , comprising a resistive discharge path couplable to the first capacitor under control of the second and third switches to provide the discharge profile of the simulator. 9. The simulator of claim 1 , wherein the power source, the first capacitor, and the least first, second and third switches comprise a first open-circuit voltage profile generator, the simulator comprising at least one second open-circuit voltage profile generator couplable in parallel with the first open-circuit voltage profile generator under control of the controller. 10. The simulator of claim 1 , wherein at least one of the at least first, second and third switches comprises an N-MOSFET. 11. The simulator of claim 1 , wherein at least one of the at least first, second and third switches comprises a P-MOSFET. 12. The simulator of claim 1 , wherein at least one of the at least first, second and third switches comprises a pair of N-MOSFETs. 13. An open-circuit output voltage profile simulator comprising: a piezoelectric power source configured to provide an open-circuit output voltage; a first capacitor; at least first, second and third switches; a controller for controlling the first, second and third switches, and a resistive discharge path couplable to the first capacitor under control of the second and third switches to provide the discharge profile of the simulator; wherein the first capacitor is coupled to the power source through the first switch to control a charge profile of the simulator, wherein the second and third switch are coupled to the first capacitor to control a discharge profile of the simulator, and wherein the resistive discharge path comprises a resistor coupled in series between the first and second switches. 14. An open-circuit output voltage profile simulator comprising: a piezoelectric power source configured to provide an open-circuit output voltage; a first capacitor; at least first, second and third switches; a controller for controlling the first, second and third switches, and a resistive discharge path couplable to the first capacitor under control of the second and third switches to provide the discharge profile of the simulator; wherein the first capacitor is coupled to the power source through the first switch to control a charge profile of the simulator, wherein the second and third switch are coupled to the first capacitor to control a discharge profile of the simulator, and wherein the resistive discharge path comprises a resistor coupled in series between the second and third switches.
Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title
Circuits; Control arrangements or methods · CPC title
Electricity · mapped topic
Electricity · mapped topic
Circuitry or processes for operating piezoelectric or electrostrictive devices not otherwise provided for, e.g. drive circuits · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.