Systems and methods for isolating input/output computing resources

Patent metadata

Field	Value
Publication number	US-10853277-B2
Application number	US-201515573114-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jun 24, 2015
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include logic to identify a Process Address Space Identifier (PASID) for a process or container of the host device and logic to associate the PASID with an individual queue pair of a hardware device of the host device, wherein the queue pair includes two complementary queues and wherein the queue pair is owned by the process or container upon association with the PASID. Other embodiments may be disclosed and/or claimed.

First claim

What is claimed is:

1. A host device for parallel computing, comprising:
a plurality of processor cores to execute a plurality of processes or containers in parallel;
first logic operated by the processor cores to identify a Process Address Space Identifier (PASID) for one of the processes or containers; and
second logic operated by the processor cores to associate the PASID with a first individual queue pair of a first plurality of queue pairs of a first input/output (I/O) hardware device communicatively coupled with the host device, and associate the PASID with a second individual queue pair of a second plurality of queue pairs of a second I/O hardware device communicatively coupled with the host device, to isolate the first individual queue pair from other ones of the first plurality of queue pairs of the first I/O hardware device and the second individual queue pair from other ones of the second plurality of queue pairs of the second I/O hardware device to form an isolated I/O hardware device partition for the process or container, with other processes or containers having respective other isolated I/O hardware device partitions having other queue pairs of the first, the second or other I/O hardware devices;
wherein each of the first and second plurality of queue pairs includes two complementary queues and wherein each of the first and second individual queue pairs is owned by the process or container upon association with the PASID of the process or container.

2. The host device of claim 1 , wherein the first logic is to, as part of association of the PASID with the first and second individual queue pairs, cause storage of the PASID into first and second PASID registers of the first and second I/O hardware devices respectively associated with the first and second individual queue pairs.

3. The host device of claim 2 , wherein the first logic is to, as part of association of the PASID with the first and second individual queue pairs, respective identify the first and second individual queue pairs as unused queue pairs from a first and a second pool of queue pairs of the first and second I/O hardware devices.

4. The host device of claim 2 , further comprising:
third logic operated by the processor cores to respectively set a first and a second PASID enable indicator of the first and second PASID registers to enable the first and second I/O hardware devices to include the associated PASID of the first and second queue pairs in Transaction Layer Packets (TLPs).

5. The host device claim 1 , wherein the first logic is to, as part of association of the PASID with the first and second individual queue pairs, utilize a create Input/Output (I/O) submission queue command of a driver with at least one of the first or the second I/O hardware device.

6. The host device of claim 5 , wherein the first logic is to, as part of association of the PASID with the first and second individual queue pairs, utilize a create I/O completion queue command of the driver of the at least one of the first or the second I/O hardware device.

7. The host device of claim 1 , further comprising:
fourth logic operated by the processor cores to provide a first and a second handler of the first and second individual queue pairs to the process or container, wherein the first and second handlers are not the PASID.

8. The host device of claim 1 , further comprising:
fifth logic operated by the processor cores to enable support for PASID operations of the first and second I/O hardware devices.

9. A first input/output (I/O) hardware device, comprising:
one or more processors;
a first collection of queue pairs, each queue pair having two complementary queues;
first logic operated by the one or more processors to identify a Process Address Space Identifier (PASID) associated with a first of the first collection of queue pairs, wherein the PASID is a PASID of a process or container executed by a host device communicatively coupled with the first and a second I/O hardware device, the second I/O hardware device having a second of a second collection of queue pairs associated with the PASID to join the first queue pair as part of an I/O hardware device partition isolated for the execution of the process or container by the host device in parallel with other processes or containers having respective other isolated I/O hardware device partitions having other queue pairs of the first, the second or other I/O hardware devices;
second logic operated by the one or more processors to generate a Transaction Layer Packet (TLP) including the PASID; and
third logic operated by the one or more processors to provide the TLP to the host device as part of a Direct Memory Access (DMA) transaction for the process or container.

10. The first I/O hardware device of claim 9 , further comprising:
a PASID Capability Register;
a first plurality of PASID registers respectively associated with the first collection of queue pairs; and
fourth logic operated by the one or more processors to, prior to identification of the PASID as associated with the first queue pair, determine that a PASID Extended Capability indicator of the PASID Capability Register is set, and determine that a PASID enable indicator of a first of the first plurality of PASID registers associated with the first queue pair is set.

11. The first I/O hardware device of claim 9 , wherein the host device is to use the PASID to determine a location of a first-level paging table for the process or container.

12. The hardware device of claim 11 , wherein the DMA transaction is associated with a DMA region assigned to the process or container in a Dynamic Random Access Memory (DRAM) of the host device.

13. The hardware device of claim 9 , wherein the first logic is to, as part of identification of the PASID associated with the first queue pair, receive the PASID from the host device.

14. A method for utilizing resources of a first and a second input/output (I/O) hardware device communicatively coupled with a host device, comprising:
receiving, by the first and second I/O hardware devices, from the host device, a Process Address Space Identifier (PASID) for a process or container being executed by the host device in parallel with other processes or containers being executed by the host device; and
respectively associating, by the first and second I/O hardware device, the PASID with a first individual queue pair of a first plurality of queue pairs of the first I/O hardware device and a second individual queue pair of a second plurality of queue pairs of the second I/O hardware device, wherein each of the first and the second queue pair includes two complementary queues, and wherein the first and second queue pairs are owned by the process or container upon association with the PASID, and are part of an I/O partition associated with the process or container;
wherein other individual queue pairs of the first and second plurality of queue pairs of the first and second I/O hardware devices are selectively associated with the other processes or containers executed in parallel via their respective PASIDs to form respective I/O partitions for the other processes or containers being executed in parallel.

15. The method of claim 14 , comprising, as part of associating the PASID of the process or container with the first and second individual queue pairs, causing storage of the PASID of the process or container into respective first and second PASID registers of the first and second I/O hardware devices respectively associated with the first and second queue pairs.

16. The method of claim 14 , further compris

Assignees

• Intel Corp

Inventors

• Liang Cunming
• Zhou Danny Y
• Cohen David E
• Harris James R

Classifications

• G06F9/5011

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title

• G06F3/00

  Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title