Method and apparatus for determining control parameters of cancellation branch, and touch control detection apparatus

Patent metadata

Field	Value
Publication number	US-10852888-B2
Application number	US-201916421477-A
Country	US
Kind code	B2
Filing date	May 24, 2019
Priority date	Dec 13, 2017
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A method and an apparatus for determining a control parameter of a cancellation branch, and a touch control detection apparatus are provided. The method includes: inputting a first constant signal to the cancellation branch, and inputting a first excitation signal to a self-capacitance detection branch, and performs differential processing for an output signal to obtain a first output signal; determining, based on the first output signal, a sum of phase delays; inputting a second constant signal to the self-capacitance detection branch, and inputting a second excitation signal to the cancellation branch, and performs differential processing for the output signal to obtain a second output signal; determining, based on the second output signal, a phase delay; and determining the control parameter of the cancellation branch based on the sum of phase delays and the phase delay.

First claim

What is claimed is:

1. A method for determining a control parameter of an offset branch of an electric circuit, comprising:
inputting a first constant signal to the offset branch, and inputting a first excitation signal to a self-capacitance detection branch, wherein a rear-end processing circuit of the self-capacitance detection branch at least performs differential processing for an output signal of the offset branch and an output signal of the self-capacitance detection branch to obtain a first output signal;
obtaining, based on the first output signal, a sum of phase delays generated by the self-capacitance detection branch and the rear-end processing circuit of the self-capacitance detection branch in response to the first excitation signal;
inputting a second constant signal to the self-capacitance detection branch, and inputting a second excitation signal to the offset branch, wherein the rear-end processing circuit of the self-capacitance detection branch at least performs differential processing for an output signal of the offset branch and the output signal of the self-capacitance detection branch to obtain a second output signal;
obtaining, based on the second output signal, a phase delay generated by the rear-end processing circuit in response to the second excitation signal; and
obtaining the control parameter of the offset branch based on the sum of phase delays and the phase delay generated by the rear-end processing circuit in response to the second excitation signal, wherein the control parameter of the offset branch is resistor and capacitor values.

2. The method according to claim 1 , wherein the first constant signal is a first direct current bias signal, and the second constant signal is a second direct current bias signal.

3. The method according to claim 1 , wherein the first constant signal is a first direct current bias signal, or the second constant signal is a second direct current bias signal.

4. The method according to claim 1 , wherein the first excitation signal and the second excitation signal have the same frequency and starting phase.

5. The method according to claim 1 , wherein the control parameter of the offset branch comprises a resistance of an adjustable resistor and a capacitance of an adjustable capacitor; wherein the adjustable resistor and the adjustable capacitor are configured to cancel or reduce a resistance of a front-end RC network in the self-capacitance detection branch and an original reference value of a to-be-detected self-capacitor.

6. The method according to claim 1 , wherein an RC network in the offset branch is configured as a pure impedance network or an approximately pure impedance network during determining the phase delay generated by the rear-end processing circuit in response to the second excitation signal.

7. The method according to claim 1 , wherein the determining, based on the first output signal, a sum of phase delays generated by the self-capacitance detection branch and the rear-end processing circuit of the self-capacitance detection branch in response to the first excitation signal comprises:
determining, based on an amplitude and a phase of the first output signal, the sum of phase delays generated by the self-capacitance detection branch and the rear-end processing circuit of the self-capacitance detection branch in response to the first excitation signal.

8. The method according to claim 7 , wherein the determining, based on the first output signal, a sum of phase delays generated by the self-capacitance detection branch and the rear-end processing circuit of the self-capacitance detection branch in response to the first excitation signal further comprises:
performing demodulation and integration processing for the first output signal to obtain a first in-phase signal and a first quadrature signal; and
determining the amplitude and the phase of the first output signal based on the first in-phase signal and the first quadrature signal.

9. The method according to claim 1 , wherein the determining, based on the second output signal, a phase delay generated by the rear-end processing circuit in response to the second excitation signal comprises:
determining, based on an amplitude and a phase of the second output signal, the phase delay generated by the rear-end processing circuit in response to the second excitation signal.

10. The method according to claim 9 , wherein the determining, based on the second output signal, a phase delay generated by the rear-end processing circuit in response to the second excitation signal further comprises:
performing demodulation and integration processing for the second output signal to obtain a second in-phase signal and a second quadrature signal; and
determining the amplitude and the phase of the second output signal based on the second in-phase signal and the second quadrature signal.

11. The method according to claim 1 , wherein the determining the control parameter of the offset branch based on the sum of phase delays and the phase delay generated by the rear-end processing circuit in response to the second excitation signal comprises:
determining, based on the sum of phase delays and the phase delay generated by the rear-end processing circuit in response to the second excitation signal, the phase delay generated by the self-capacitance detection branch in response to the first excitation signal; and
determining the control parameter of the offset branch based on the phase delay generated by the self-capacitance detection branch in response to the first excitation signal.

12. The method according to claim 11 , wherein the determining the control parameter of the offset branch based on the phase delay generated by the self-capacitance detection branch in response to the first excitation signal comprises:
establishing an association relationship between a front-end RC network in the self-capacitance detection branch and an RC network in the offset branch based on the phase delay generated by the self-capacitance detection branch in response to the first excitation signal; and
determining the control parameter of the offset branch based on the association relationship between the front-end RC network in the self-capacitance detection branch and the RC network in the offset branch.

13. The method according to claim 12 , wherein the control parameter of the offset branch comprises a first control parameter and a second control parameter, and correspondingly, the determining the control parameter of the offset branch based on an association relationship between the front-end RC network in the self-capacitance detection branch and the RC network in the offset branch comprises:
determining the second control parameter of the offset branch based on the association relationship between the front-end RC network in the self-capacitance detection branch and the RC network in the offset branch, and a predefined first control parameter of the offset branch.

14. The method according to claim 1 , wherein the rear-end processing circuit comprises at least one of: an amplifier, a filter and an analog-to-digital converter; wherein the amplifier is configured to perform differential processing for the output signal of the self-capacitance detection branch and the output signal of the offset branch, the filter is configured to perform filtering processing for signals upon the differential processing, and the analog-to-digital converter is configured to perform analog-to-digital conversion for signals upon the filtering.

15. An apparatus for determining a control parameter of an offset branch of an electric circuit, c

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Fang Jun
• Liao Guanliang
• Yang Yang
• Yao Zhi

Classifications

• G06F3/0418 Primary

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G01R27/2605 Primary

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title

• G06F3/044

  by capacitive means · CPC title