Adaptive power down of intra-chip interconnect

Patent metadata

Field	Value
Publication number	US-10852810-B2
Application number	US-201916294755-A
Country	US
Kind code	B2
Filing date	Mar 6, 2019
Priority date	Jun 13, 2017
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

An integrated circuit comprising a plurality of last-level caches, a plurality of processor cores configured to access data in the plurality of last-level caches, and an interconnect network. The plurality of last-level caches can be placed in at least a high cache-power consumption mode and a low cache-power consumption mode. The plurality of last-level caches includes a first last-level cache and a second last-level cache. The interconnect network comprises a plurality of links that can be placed in at least a high link-power consumption mode and a low link-power consumption mode. The interconnect network is configured to cause a first subset of the plurality of links to be placed in the low link-power consumption mode based at least in part on the first last-level cache being in the low cache-power consumption mode.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a plurality of last-level caches that can be placed in at least a high cache-power consumption mode and a low cache-power consumption mode, the plurality of last-level caches including a first last-level cache and a second last-level cache;
a plurality of processor cores configured to access data in the plurality of last-level caches; and
an interconnect network, comprised of a plurality of links that can be placed in at least a high link-power consumption mode and a low link-power consumption mode, the interconnect network configured to receive access addresses from the plurality of processor cores and to couple, via respective subsets of the plurality of links, each of the plurality of processor cores to a respective one of the plurality of last-level caches, and to cause a first subset of the plurality of links to be placed in the low link-power consumption mode based at least in part on the first last-level cache being in the low cache-power consumption mode.

2. The integrated circuit of claim 1 , wherein the plurality of links is connected in a fully-connected mesh topology.

3. The integrated circuit of claim 1 , wherein the plurality of links is connected in a star topology.

4. The integrated circuit of claim 1 , wherein the plurality of links is connected in a ring topology.

5. The integrated circuit of claim 1 , wherein the plurality of links is connected in a crossbar topology.

6. The integrated circuit of claim 1 , wherein the plurality of links is connected in a hybrid topology including network portions having one or more of a mesh topology, a star topology, a ring topology, and a crossbar topology.

7. The integrated circuit of claim 1 , wherein the plurality of links includes one or more point-to-point links.

8. A method of operating a processing system having a plurality of processor cores, comprising:
based at least in part on an initial portion of a cache being in an available power consumption mode and an alternate portion of the cache being in a reduced power consumption mode, routing accesses to the cache by a first processor core of the plurality of processor cores via the initial portion of the cache; and
based at least in part on the alternate portion of the cache being placed in the available power consumption mode, routing accesses to the cache by the first processor core via the alternate portion of the cache.

9. The method of claim 8 , wherein the alternate portion of the cache is associated with a second processor core, the method further comprising placing the alternate portion of the cache in the available power consumption mode responsive to the second processor core being in the available power consumption mode.

10. The method of claim 8 , wherein the alternate portion of the cache is associated with a second processor core, the method further comprising placing the second processor core in the available power consumption mode responsive to alternate portion of the cache being in the available power consumption mode.

11. The method of claim 8 , wherein routing accesses to the cache is controlled by a hash function, and wherein the hash function is changed according to whether the alternate portion of the cache is in the available power consumption mode.

12. The method of claim 8 , wherein the alternate portion of the cache includes one or more of a circuit link and a last-level cache, and the initial portion of the cache excludes one or both of the circuit link and the last-level cache.

13. The method of claim 12 , further comprising, while the last-level cache is in the available power consumption mode, placing the circuit link in the available power consumption mode.

14. The method of claim 12 , wherein routing accesses to the cache is controlled by a hash function, and wherein the hash function is changed according to whether zero, one, or both of the last-level cache and the circuit link are in the available power consumption mode.

15. A method of operating a plurality of processor cores on an integrated circuit, comprising:
distributing accesses by a first processor core to a cache via an initial portion of the cache including one or more of a circuit link and a last-level cache associated with the first processor core;
distributing accesses by a second processor core to the cache via the initial portion of the cache;
placing one or both of the circuit link and the last-level cache in a reduced power consumption mode; and,
while one or both of the circuit link and the last-level cache is in the reduced power consumption mode, distributing accesses by the second processor core to the cache via an alternate portion of the cache that excludes one or both of the circuit link and the last-level cache.

16. The method of claim 15 , further comprising placing one or both of the circuit link and the last-level cache in the reduced power consumption mode responsive to the first processor core being in the reduced power consumption mode.

17. The method of claim 15 , further comprising placing the first processor core in the reduced power consumption mode responsive to one or both of the circuit link and the last-level cache being in the reduced power consumption mode.

18. The method of claim 15 , further comprising placing the circuit link in the reduced power consumption mode responsive to the last-level cache being in the reduced power consumption mode.

19. The method of claim 18 , wherein the circuit link is one of a set of circuit links associated with the last-level cache, the method further comprising placing the set of circuit links in the reduced power consumption mode.

20. The method of claim 15 , wherein distributing accesses to the cache is controlled by a hash function, and wherein the hash function is changed according to whether zero, one, or both of the last-level cache and the circuit link are in the reduced power consumption mode.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lai Patrick P
• Shearer Robert Allen

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title