Relative height adjustable connector system for motherboard to graphics board transition with a plating alternative in information handling systems

US10852783B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10852783-B2
Application numberUS-201815951115-A
CountryUS
Kind codeB2
Filing dateApr 11, 2018
Priority dateApr 11, 2018
Publication dateDec 1, 2020
Grant dateDec 1, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system and method of operatively coupling a motherboard and a graphics board supported on a chassis, coating the motherboard and the graphics board with an anti-tarnish finish, plating a first interposer on at least a first side with a neutral metal material, soldering pass-through electrical contacts of the first interposer to a connector pad area of the motherboard, and clamping a first compression jumper pad to compress an array of compressible communication contacts to the pass-through electrical contacts on the first interposer, adjusting a flexible jumper trace array cable between the first compression jumper pad and a second compression jumper pad to adjacently align the motherboard and graphics board to minimize thickness of the information handling system, and coupling the second compression jumper pad to the graphics board to provide lanes of data communication.

First claim

Opening claim text (preview).

What is claimed is: 1. An information handling system comprising: a chassis supporting a motherboard having a processor and a graphics board including a graphics processor, wherein the motherboard and the graphics board are coated with an anti-tarnish material; a first interposer soldered to a connector pad area of the motherboard, wherein the first interposer has at least one side plated with a neutral metal material; a flexible compression jumper connector having a first compression jumper pad with a first array of compressible communication contacts operatively coupled to the first interposer; a first fastener to compress the first array of compressible communication contacts to a plurality of pass-through electrical contacts on the first interposer; and the flexible compression jumper connector having a flexible jumper trace array cable between the first compression jumper pad and a second compression jumper pad operatively coupled to the graphics board such that the motherboard and the graphics board are operatively coupled with lanes of data communication between the processor and the graphics processor, wherein the flexible jumper trace array cable may be adjusted to align the motherboard adjacent to the graphics board to reduce thickness of the information handling system. 2. The system of claim 1 , further comprising: a second interposer soldered to a connector pad area of the graphics board, wherein the second interposer has at least one side plated with a neutral metal material; the second compression jumper pad with a second array of compressible communication contacts operatively coupled to the connector pad area of the graphics board via the second interposer; and a second fastener to compress the second array of compressible communication contacts to the plurality of pass-through electrical contacts on the second interposer. 3. The system of claim 2 , wherein the first fastener and the second fastener are compression screws disposed through the first compression jumper pad and the second compression jumper pad respectively. 4. The system of claim 1 , wherein the first array of compressible communication contacts is an array of electrical spring contacts making electrical contact when compressed to the first interposer. 5. The system of claim 1 , wherein the first connector pad interface area with a plurality of electrical contacts on the motherboard includes an array of electrical contacts on the motherboard corresponding to the plurality of pass-through electrical contacts on the first interposer which correspond to the first array of compressible communication contacts of the first compression jumper pad. 6. The system of claim 1 , wherein the least one side of the first interposer is plated with the neutral metal that includes electroless nickel immersion gold (ENIG). 7. A method of operatively coupling a motherboard and a graphics board in an information handling system comprising: supporting the motherboard including a central processor and the graphics board including a graphics processor on a chassis, wherein the motherboard and the graphics board are coated with an anti-tarnish finish; plating a first interposer on at least a first side with a neutral metal material; soldering a first plurality of pass-through electrical contacts of the first interposer to a connector pad area of the motherboard; aligning a first compression jumper pad of a flexible compression jumper connector with the first plurality of pass-through electrical contacts on the plated first side of the first interposer; clamping the first compression jumper pad with a first fastener to compress an array of compressible communication contacts on the first compression jumper pad to the first plurality of pass-through electrical contacts on the first interposer; adjusting a flexible jumper trace array cable between the first compression jumper pad and a second compression jumper pad of the flexible compression jumper connector to adjacently align the motherboard and graphics board to minimize thickness of the information handling system; and operatively coupled the second compression jumper pad of the flexible compression jumper connector to the graphics board, via a second fastener, to provide lanes of data communication between the central processor and the graphics processor. 8. The method of claim 7 , further comprising: setting the relative height of the graphics board adjacent to the motherboard such that a top of the central processor and a top of the graphics processor align in height relative to the bottom of the chassis; and operatively couple a planar heat pipe to the top of the central processor and the top of the graphics processor. 9. The method of claim 7 , wherein soldering the first interposer to a connector pad area of the motherboard further comprises applying solder paste to the first plurality of pass-through electrical contacts on a second side of the first interposer, aligning the second side of the first interposer with the connector pad interface area of the motherboard, and applying heat to affix the solder between the second side of the first interposer and the motherboard. 10. The method of claim 7 , wherein clamping the first compression jumper pad to compress an array of compressible communication contacts to the first plurality of pass-through electrical contacts on the first interposer includes disposing the first fastener comprising a compression screw through the first compression jumper pad of the flexible compression jumper connector and into a compression screw nut disposed below the first interposer. 11. The method of claim 7 , further comprising: soldering a second interposer to a connector pad area of the graphics board, wherein the second interposer is plated with a neutral metal material on a side opposite of the solder; clamping the second compression jumper pad to compress a second array of compressible communication contacts to a second plurality of pass-through electrical contacts on the second interposer plated with the neutral metal material. 12. An information handling system comprising: a chassis supporting a motherboard having a processor and a graphics board including a graphics processor, wherein the motherboard and the graphics board are coated with an anti-tarnish material; a first interposer soldered to a connector pad area of the motherboard, wherein the first interposer has at least one side plated with a neutral metal material; a flexible compression jumper connector having a first compression jumper pad with a first array of compressible communication contacts operatively coupled to the first interposer; a first fastener to compress the first array of compressible communication contacts to a plurality of pass-through electrical contacts on the first interposer; a second fastener to compress a second array of compressible communication contacts of a second compression jumper pad to a connector pad area of the graphics board; and the flexible compression jumper connector having a flexible jumper trace array cable between the first compression jumper pad and the second compression jumper pad operatively coupled to the graphics board such that the motherboard and the graphics board are operatively coupled with lanes of data communication between the processor and the graphics processor, wherein the flexible jumper trace array cable may be adjusted to align the motherboard adjacent to the graphics board to reduce thickness of the information handling system. 13. The system of claim 12 , further comprising: a second interposer soldered to the connector pad area of the graphics board, wherein th

Assignees

Inventors

Classifications

  • Structural association of two or more printed circuits (providing electric connection to or between printed circuits H05K1/11, H01R12/00) · CPC title

  • Interposers · CPC title

  • for portable computers, e.g. for laptops · CPC title

  • Mounting of expansion boards · CPC title

  • G06F1/184Primary

    Mounting of motherboards · CPC title

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What does patent US10852783B2 cover?
A system and method of operatively coupling a motherboard and a graphics board supported on a chassis, coating the motherboard and the graphics board with an anti-tarnish finish, plating a first interposer on at least a first side with a neutral metal material, soldering pass-through electrical contacts of the first interposer to a connector pad area of the motherboard, and clamping a first com…
Who is the assignee on this patent?
Dell Products Lp
What technology area does this patent fall under?
Primary CPC classification G06F1/184. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).