Multi-socket server assembly

US10849223B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10849223-B2
Application numberUS-201916294277-A
CountryUS
Kind codeB2
Filing dateMar 6, 2019
Priority dateMar 6, 2019
Publication dateNov 24, 2020
Grant dateNov 24, 2020

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In some examples, a printed circuit board assembly can include a printed circuit board having four (4) central processor unit (CPU) sockets disposed thereon and sixty four (64) dual in-line memory modules (DIMMs) disposed thereon. The printed circuit board can have a top surface and a bottom surface with two (2) CPU sockets and thirty two (32) DIMMs disposed on the top surface and two (2) CPU sockets and thirty two (32) DIMMs disposed on the bottom surface.

First claim

Opening claim text (preview).

What is claimed is: 1. A printed circuit board comprising: a top surface and a bottom surface; a plurality of processor sockets disposed on the printed circuit board; a first plurality of dual in-line memory modules (DIMMs) disposed on the top surface; and a second plurality of DIMMs disposed on the bottom surface; wherein a first contact area of each DIMM in the first plurality of DIMMs and a second contact area of each DIMM in the second plurality of DIMMs have a respective overlapping alignment along a vector that is perpendicular to a plane of the printed circuit board, wherein each pair of DIMMs associated with the first contact area and the second contact area having the respective overlapping alignment is connected to a respective processor through a single via. 2. The printed circuit board of claim 1 , wherein each pair of DIMMs comprises a first DIMM and a second DIMM having the first contact area and the second contact area with the respective overlapping alignment. 3. The printed circuit board of claim 2 , wherein each processor socket is coupled with one or more pairs of DIMMs comprise a number of DIMMs disposed on the top surface and the number of DIMMs disposed on the bottom surface. 4. The printed circuit board of claim 2 , wherein each pair of DIMMs is coupled with the respective processor socket by a single channel. 5. The printed circuit board of claim 1 , wherein one or more processor sockets disposed on the top surface are longitudinally displaced from one or more processor sockets disposed on the bottom surface. 6. The printed circuit board of claim 1 , wherein one or more processor sockets disposed on the top surface are laterally displaced, one from one or more other processor sockets and one or more processor sockets disposed on the bottom surface are laterally displaced from one or more different processor sockets. 7. The printed circuit board of claim 6 , wherein a cooling path extends longitudinally across the printed circuit board, thus laterally displaced processor sockets interact with the cooling path. 8. The printed circuit board of claim 1 , wherein the plurality of processor sockets comprises at least 4 sockets, wherein the first plurality of DIMMs comprises at least 32 DIMMs and the second plurality of DIMMs comprises at least 32 DIMMs, the printed circuit board being housed in a 7U housing. 9. The printed circuit board of claim 1 , wherein each processor socket in the plurality of processor sockets has a plurality of high speed links, each high speed link coupling the processor socket with each remaining processor socket in the plurality of processor sockets. 10. The printed circuit board of claim 1 , wherein each processor socket in the plurality of processor sockets has a plurality of high speed links and wherein each processor socket is coupled with each remaining processor socket in the plurality of processor sockets via two high speed links from the plurality of high speed links. 11. A system assembly comprising: a housing; and a printed circuit board within the housing, the printed circuit board comprising: a top surface and a bottom surface; a plurality of processor sockets disposed on the printed circuit board; a first plurality of dual in-line memory modules (DIMMs) disposed on the top surface; and a second plurality of DIMMs disposed on the bottom surface; wherein a first contact area of each DIMM in the first plurality of DIMMs and a second contact area of each DIMM in the second plurality of DIMMs have a respective overlapping alignment along a vector that is perpendicular to a plane of the printed circuit board, wherein each set of DIMMs associated with the first contact area and the second contact area having the respective overlapping alignment is connected to a respective processor through a single via. 12. The system assembly of claim 11 , wherein each set of DIMMs comprises a first DIMM and a second DIMM having the first contact area and the second contact area with the respective overlapping alignment. 13. The system assembly of claim 12 , wherein each processor socket is coupled with one or more sets of DIMMs comprising a number of, DIMMs disposed on the top surface and the number of DIMMs disposed on the bottom surface. 14. The system assembly of claim 12 , wherein each set of DIMMs is coupled with the respective processor socket by a single channel. 15. The system assembly of claim 11 , wherein the first plurality of processor sockets on the top surface are longitudinally displaced from the second plurality of processor sockets on the bottom surface. 16. The system assembly of claim 11 , wherein the first plurality of processor sockets on the top surface are laterally displaced from each other and the second plurality of processor sockets on the bottom surface are laterally displaced from each other. 17. The system assembly of claim 16 , wherein a cooling path extends longitudinally across the printed circuit board, thus laterally displaced processor sockets interact with the cooling path. 18. The system assembly of claim 11 , wherein each processor socket in the first plurality of processor sockets and in the second plurality of processor sockets has a plurality of high speed links, each high speed link coupling each processor socket with each remaining processor socket in the first plurality of processor sockets and the second plurality of processor sockets. 19. The system assembly of claim 11 , wherein each processor socket in the first plurality of processor sockets and the second plurality of sockets has a plurality of high speed links, each two high speed links coupling the processor socket with each remaining processor socket in the first plurality of processor sockets and the second plurality of processor sockets. 20. The system assembly of claim 11 , further comprising an airflow path arranged to pass over both the top surface and the bottom surface.

Assignees

Inventors

Classifications

  • for multiple cards · CPC title

  • Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support · CPC title

  • H05K1/11Primary

    Printed elements for providing electric connections to or between printed circuits · CPC title

  • within server blades for removing heat from heat source · CPC title

  • G06F1/20Primary

    Cooling means · CPC title

Patent family

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Frequently asked questions

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What does patent US10849223B2 cover?
In some examples, a printed circuit board assembly can include a printed circuit board having four (4) central processor unit (CPU) sockets disposed thereon and sixty four (64) dual in-line memory modules (DIMMs) disposed thereon. The printed circuit board can have a top surface and a bottom surface with two (2) CPU sockets and thirty two (32) DIMMs disposed on the top surface and two (2) CPU s…
Who is the assignee on this patent?
Cisco Tech Inc
What technology area does this patent fall under?
Primary CPC classification H05K1/11. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 24 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).