Phase interpolator

Patent metadata

Field	Value
Publication number	US-10848299-B2
Application number	US-201916728487-A
Country	US
Kind code	B2
Filing date	Dec 27, 2019
Priority date	Dec 29, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A phase interpolator includes a phase adjusting circuit. The phase adjusting circuit includes a first phase adjusting module and a second phase adjusting module, the first phase adjusting module outputs a first clock signal, and the second phase adjusting module outputs a second clock signal; the first phase adjustment module and the second phase adjustment module are connected in parallel to output an interpolation signal. Through the first phase adjustment module and the second phase adjustment module the first clock signal and the second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.

First claim

What is claimed is:

1. A phase interpolator, comprising:
a phase adjusting circuit comprising a first phase adjusting module and a second phase adjusting module, the first phase adjusting module outputting a first clock signal, and the second phase adjusting module outputting a second clock signal;
the first phase adjusting module and the second phase adjusting module are connected in parallel to output an interpolation signal;
wherein each of the first phase adjusting module and the second phase adjusting module comprises:
a signal input end;
a signal output end;
a first MOS transistor, wherein a gate of the first MOS transistor is connected to the signal input end, a drain of the first MOS transistor is connected to a VCC (Volt Current Condenser), and a source of the first MOS transistor is connected to a first fulcrum;
a first adjusting module, connected between the first fulcrum and the signal output end;
a second MOS transistor, wherein a gate of the second MOS transistor is connected to the signal input end, a source of the second MOS transistor is connected to a ground (GND), and a drain of the second MOS transistor is connected to a second fulcrum; and
a second adjusting module, connected between the second fulcrum and the signal output end.

2. The phase interpolator of claim 1 , wherein the phase interpolator further comprises a low-pass filter circuit, an input end of the low-pass filter circuit is connected to an output end of the phase adjusting circuit, the low-pass filter circuit is configured to filter a high-frequency signal of the interpolation signal.

3. The phase interpolator of claim 2 , wherein the phase interpolator further comprises a shaping circuit, an input end of the shaping circuit is connected to an output end of the low-pass filter circuit, the shaping circuit is configured to shape the interpolation signal output by the low-pass filter circuit, so as to output a required interpolation signal.

4. The phase interpolator of claim 1 , wherein the first adjusting module comprises a plurality of first adjusting circuits, each of which is connected between the first fulcrum and the signal output end.

5. The phase interpolator of claim 4 , wherein each of the plurality of first adjusting circuits comprises:
a first switch tube, wherein a drain of the first switch tube is connected to the first fulcrum; and
a first resistor, connected between a source of the first switch tube and the signal output end.

6. The phase interpolator of claim 1 , wherein the second adjusting module comprises a plurality of second adjusting circuits, each of which is connected between the second fulcrum and the signal output end.

7. The phase interpolator of claim 6 , wherein each of the plurality of second adjusting circuits comprises:
a second switch tube, wherein a source of the second switch tube is connected to the second fulcrum; and
a second resistor, connected between a drain of the second switch tube and the signal output end.

8. The phase interpolator of claim 5 , wherein both the first MOS transistor and the first switch tube are N-type MOS transistors.

9. The phase interpolator of claim 7 , wherein both the second MOS transistor and the second switch tube are P-type MOS transistors.

10. The phase interpolator of claim 1 , wherein each of the first phase adjusting module and the second phase adjusting module comprises:
a third MOS transistor, wherein a gate of the third MOS transistor is connected to the signal input end, a drain of the third MOS transistor is connected to a third fulcrum, and a source of the third MOS transistor is connected to the signal output end;
a third adjusting module, connected between the third fulcrum and a VCC;
a fourth MOS transistor, wherein a gate of the fourth MOS transistor is connected to the signal input end, a source of the fourth MOS transistor is connected to a fourth fulcrum, and a drain of the fourth MOS transistor is connected to the signal output end; and
a fourth adjusting module, connected between the fourth fulcrum and the ground.

11. The phase interpolator of claim 10 , wherein the third adjusting module comprises a plurality of third adjusting circuits, each of which is connected between the third fulcrum and the VCC.

12. The phase interpolator of claim 11 , wherein each of the plurality of third adjusting circuits comprises:
a third switch tube, wherein a drain of the third switch tube is connected to the VCC; and
a third resistor, connected between a source of the third switch tube and the third fulcrum.

13. The phase interpolator of claim 10 , wherein the fourth adjusting module comprises a plurality of fourth adjusting circuits, each of which is connected between the fourth fulcrum and the ground.

14. The phase interpolator of claim 13 , wherein each of the plurality of fourth adjusting circuits comprises:
a fourth switch tube, wherein a source of the fourth switch tube is connected to the ground; and
a fourth resistor, connected between a drain of the fourth switch tube and the fourth fulcrum.

15. The phase interpolator of claim 12 , wherein both the third MOS transistor and the third switch tube are N-type MOS transistors.

16. The phase interpolator of claim 14 , wherein both the fourth MOS transistor and the fourth switch tube are P-type MOS transistors.

Assignees

• Amlogic Shanghai Co Ltd

Inventors

• Shi Ming

Classifications

• H03K2005/00052

  by mixing the outputs of fixed delayed signals with each other or with the input signal · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• H04L7/0337 Primary

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title