Probabilistic shaping techniques for high performance coherent optical transceivers

Patent metadata

Field	Value
Publication number	US-10848249-B2
Application number	US-202016797704-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Jan 24, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.

First claim

What is claimed is:

1. A method of operating a communication device having a distribution matcher encoder module and a distribution matcher decoder module electrically coupled by a channel module, the method comprising:
receiving, by n encoder function blocks of the distribution matcher encoder module coupled in series and configured to convert data from a first form (x) to a second form (b), the following inputs: data x, a code length n, and a bits per codeword n′;
storing, by a plurality of encoder storage units of the series of encoder function blocks, the following initial values: a n =x and n n ′=n′;
performing, by the series of encoder function blocks, the following actions for i=n−1 to 0:
when a first condition characterized by

a

i
+
1

≥

(

i

n

i
+
1

′

-
1

)

or a second condition characterized by n i+1 ′≤0 is satisfied, computing, by encoder comparison and adder circuits of the series of encoder function blocks, and storing, by the plurality of encoder storage units, the following intermediate values:

a
i

=

a

i
+
1

-

(

i

n

i
+
1

′

-
1

)

,

b i =0, and n i ′=n i+1 ′; and
when neither the first condition nor the second condition is satisfied, computing, by the encoder comparison and adder circuits, and storing, by the plurality of encoder storage units, the following intermediate values: a i =a i+1 , b i =1, and n i ′=n i+1 ′−1;
outputting, by the series of encoder function blocks, converted data b;
receiving, by n decoder function blocks of the distribution matcher decoder module coupled in series and configured to convert data from the second form to the first form, the converted data b, the code length n, and the bits per codeword n′ as inputs;
storing, by a plurality of decoder storage units of the series of decoder function blocks, the following initial values: a n =0 and n n ′=n′;
performing, by the series of decoder function blocks, the following actions for i=n−1 to 0:
when a first condition characterized by b 1 ==1 or a second condition characterized by n i+1 ′==0 is satisfied, computing, by decoder comparison and adder circuits of the series of decoder function blocks, and storing, by the plurality of decoder storage units, the following intermediate value: a i =a i+1 ;
when neither the first condition nor the second condition is satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value:

a
i

=

a

i
+
1

+

(

i

n

i
+
1

′

-
1

)

;

when the first condition is satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value: n i ′=n i+1 ′−1; and
when the first condition is not satisfied, computing, by the decoder comparison and adder circuits, and storing, by the plurality of decoder storage units, the following intermediate value: n i ′=n i+1 ′;
storing, by the plurality of decoder storage units, the following final value: x=a 0 ; and
outputting, by the series of decoder function blocks, restored data x.

2. The method of claim 1 wherein computing, by the encoder comparison and adder circuits, the intermediate values includes computing, by one or more carry save adders of each of the encoder function blocks, the intermediate values.

3. The method of claim 1 further comprising
splitting, by a splitter module electrically coupled to the distribution matcher encoder module, input data into random data and controlled data; and
sending, by the splitter module, the controlled data to the distribution matcher encoder module and the random data to a forward error correction (FEC) encoder module.

4. The method of claim 1 wherein computing, by the decoder comparison and adder circuits, the intermediate values includes computing, by one or more carry save adders of each of the decoder function blocks, the intermediate values.

5. The method of claim 1 further comprising
receiving, by a mapper module electrically coupled to the channel module and to a forward error correction (FEC) encoder module that is electrically coupled to the distribution matcher encoder module, encoded controlled data and encoded random data from the FEC encoder module;
outputting, by the mapper module, the encoded controlled data and the encoded random data as 2D symbols to the channel module;
receiving, by a demapper module electrically coupled to the channel module and to an FEC decoder module that is electrically cou

Assignees

• Inphi Corp

Inventors

• Morero Damian Alfonso
• Castrillon Mario Alejandro
• Lopez Ramiro Rogelio
• Cavenio Cristian
• Infante Gabriel
• Hueda Mario Rafael

Classifications

• H04B10/616 Primary

  Details of the electronic signal processing in coherent optical receivers · CPC title

• H04J14/0298

  with sub-carrier multiplexing [SCM] · CPC title

• H04L27/34

  Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems · CPC title

• H03M7/14 Primary

  Conversion to or from non-weighted codes · CPC title

• H04L27/2275

  wherein the carrier recovery circuit uses the received modulated signals · CPC title