Analog-to-digital converter correcting frequency characteristics and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-10848173-B2
Application number	US-201916557664-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Mar 2, 2017
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

An analog-to-digital converter (ADC) includes a modulator configured to oversample an input signal generated from an output signal of a transducer; and a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of the transducer and the filter be flat in a signal band.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) comprising:
a modulator configured to oversample an input signal generated from an output signal of a transducer; and
a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator,
wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of a signal output form the ADC be flat in a signal band, and
wherein the filter control signal is externally provided.

2. The ADC of claim 1 , wherein the modulator is a sigma delta modulator (SDM).

3. The ADC of claim 1 , wherein the filter includes a decimation filter and a correction filter, wherein the correction filter is controlled according to the filter control signal and performs the frequency characteristics correction operation.

4. The ADC of claim 3 , wherein the decimation filter includes a cascaded integrator and comb (CIC) filter.

5. The ADC of claim 4 , wherein the decimation filter includes an integrator, a sample remover, and a comb filter.

6. The ADC of claim 3 , wherein each of the decimation filter and the correction filter includes a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter.

7. The ADC of claim 3 , wherein the correction filter includes:
a plurality of unit delay elements configured to sequentially delay a digital input signal;
a plurality of unit amplifiers configured to amplify the digital input signal and outputs of the plurality of unit delay elements according to the filter control signal;
an adder configured to add outputs of the plurality of unit amplifiers; and
a sample remover configured to remove one or more samples from output from the adder.

8. The ADC of claim 3 , wherein the correction filter includes:
a plurality of unit delay elements configured to sequentially delay a digital input signal;
a plurality of sample removers configured to remove one or more samples from the digital input signal and outputs of the plurality of unit delay elements;
a plurality of unit amplifiers configured to amplify outputs of the plurality of sample removers according to the filter control signal; and
an adder configured to add outputs of the plurality of unit amplifiers.

9. The ADC of claim 1 , further comprising a monitoring device configured to monitor an output of the modulator and to control the filter such a gain of an output of the ADC be substantially constant in a signal band.

10. A semiconductor device comprising:
a transducer; and
an analog-to-digital converter (ADC), wherein the ADC includes:
a modulator configured to oversample an input signal generated from an output signal of a transducer; and
a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, and
wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of a signal output from the ADC be flat in a signal band, and
wherein the filter control signal is externally provided.

11. The semiconductor device of claim 10 , wherein the modulator is a sigma delta modulator (SDM).

12. The semiconductor device of claim 10 , wherein the filter includes a decimation filter and a correction filter, wherein the correction filter is controlled according to the filter control signal and performs the frequency characteristics correction operation.

13. The semiconductor device of claim 12 , wherein the decimation filter includes a cascaded integrator and comb (CIC) filter.

14. The semiconductor device of claim 13 , wherein the decimation filter includes an integrator, a sample remover, and a comb filter.

15. The semiconductor device of claim 12 , wherein each of the decimation filter and the correction filter includes a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter.

16. The semiconductor device of claim 12 , wherein the correction filter includes:
a plurality of unit delay elements configured to sequentially delay a digital input signal;
a plurality of unit amplifiers configured to amplify the digital input signal and outputs of the plurality of unit delay elements according to the filter control signal;
an adder configured to add outputs of the plurality of unit amplifiers; and
a sample remover configured to remove one or more samples from output of the adder.

17. The semiconductor device of claim 12 , wherein the correction filter includes:
a plurality of unit delay elements configured to sequentially delay a digital input signal;
a plurality of sample removers configured to remove one or more samples from the digital input signal and outputs of the plurality of unit delay elements;
a plurality of unit amplifiers configured to amplify outputs of the plurality of sample removers according to the filter control signal; and
an adder configured to add outputs of the plurality of unit amplifiers.

18. The semiconductor device of claim 10 , further comprising a monitoring device configured to monitor an output of the modulator and to control the filter such that gain of an output of the ADC be substantially constant in a signal band.

19. The semiconductor device of claim 10 , further comprising an amplifier configured to buffer or amplify an output of the transducer and provide an output signal thereof as the input signal of the ADC.

Assignees

• Seoul Nat Univ R&Db Foundation

Inventors

• Kim Suhwan
• Cho Junsoo

Classifications

• H03M1/0626

  by filtering · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/344 Primary

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03H17/0411

  using DELTA modulation · CPC title

• H03M3/494

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title