Converter techniques for sinking and sourcing current

Patent metadata

Field	Value
Publication number	US-10848063-B2
Application number	US-201916245818-A
Country	US
Kind code	B2
Filing date	Jan 11, 2019
Priority date	Jan 11, 2019
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Techniques for a sinking and sourcing power stage are provided. In an example, a power stage circuit can include a first power transistor configured to couple to a first input power rail, a second power transistor configured to couple to a second input power rail, an output node configured to couple to a load and to couple the first power transistor in series with the second power transistor between the first and second input power rails, and a controller configured to operate the first and second power transistors in a first mode to source current to the load and to operate the first and second power transistors in a second mode to sink current from the load.

First claim

What is claimed is:

1. A method for operating a switching circuit having a first switch configured to couple to a first supply rail, a second switch configured to couple to a second supply rail and a switch node coupling the first switch in series with the second switch, and an inductor coupled between the switch node and a load, the method comprising:
triggering a first low-impedance state of the first switch on a first transition of a pulse-width modulated (PWM) signal from a first logic level to a second logic level;
triggering a first high impedance state of the first switch on a second transition of the PWM signal from the second logic level to the first logic level;
initiating a first non-overlapping interval in response to the second transition;
detecting a body diode conduction event of the first switch during the first non-overlapping interval;
commanding a first low-impedance state of the second switch in response to the body diode conduction event of the first switch; and
triggering the second switch to a first high-impedance state based on a subsequent third transition of the PWM signal from the first logic level to the second logic level.

2. The method of claim 1 , including triggering a second low-impedance state of the second switch on a subsequent fourth transition of the PWM signal from the second logic level to the first logic level.

3. The method of claim 2 , including, when the second switch is in the second low-impedance state after the fourth transition,
detecting a negative maximum current limit event when the current of the inductor violates a maximum negative current limit;
commanding a second high-impedance state of the second switch in response to the negative maximum current limit event; and
commanding a second low-impedance state of the first switch in response to the negative current limit event.

4. The method of claim 1 , including:
triggering a second high-impedance state of the second switch on a fourth transition of the PWM signal from the first logic level to the second logic level;
initiating a second non-overlapping interval in response to the fourth transition;
detecting a body diode conduction event of the second switch during the second non-overlapping interval; and
triggering the first switch to a second high-impedance state based on a subsequent fifth transition of the PWM signal from the first logic level to the second logic level.

5. The method of claim 4 , triggering a second low-impedance state of the first switch on a subsequent sixth transition of the PWM signal from the first logic level to the second logic level.

6. The method of claim 5 , including, when the first switch is in the second low-impedance state after the sixth transition,
detecting a positive maximum current limit event when the current of the inductor violates a maximum positive current limit;
commanding a third high-impedance state of the first switch in response to the positive current limit event; and
commanding a second low-impedance state of the second switch in response to the positive current limit event.

7. A power stage circuit for a switched-mode converter, the power stage comprising:
a first detector circuit to receive a signal indicative of body diode conduction of a first power transistor, the first power transistor to couple a first supply node to an intermediate node;
a second detector circuit to receive a signal indicative of body diode conduction of a second power transistor, the second power transistor to couple a second supply node to the intermediate node;
an output node to feed a load from an inductor, the inductor coupled between the output node and the intermediate node; and
a controller configured to operate the first and second power transistors to avoid body diode conduction through the first and second power transistors, the controller comprising:
first switching logic for a first mode of operation; and
second switching logic for a second mode of operation;

wherein the controller is communicatively coupled to the first and second detector circuits; and
wherein in response to a body diode conduction event indication for the first or second power transistor, control nodes of the first and second power transistors are isolated from one of the first switching logic and the second switching logic.

8. The power stage circuit of claim 7 , further comprising a multiplexer circuit configured to couple the controller to the first and second detector circuits, wherein the multiplexer circuit is configured to selectively isolate the control nodes of the first and second power transistors from one of the first switching logic or the second switching logic depending on the mode of operation.

9. The power stage circuit of claim 7 , including a current comparator configured to receive a representation of output current of the output node, to compare the representation of output current to one or more maximum current limits to provide one or more maximum current limit comparisons, and to provide an indication of each maximum current limit comparison to the controller.

10. The power stage circuit of claim 9 , wherein the controller is configured to:
trigger a first low-impedance state of the first power transistor on a first transition of a PWM signal from a first logic level to a second logic level using the first switching logic;
trigger a first high impedance state of the first power transistor on a second transition of the PWM signal from the second logic level to the first logic level using the first switching logic;
initiate a first non-overlapping interval in response to the second transition using the first switching logic;
receive the first body diode conduction event indication of the first power transistor during the first non-overlapping interval from first detector circuit;
couple the control nodes of the first and second power transistors to second switching logic using a multiplexer in response to the first body diode conduction event indication; and
trigger the second power transistor to a first high-impedance state based on a subsequent third transition of the PWM signal from the first logic level to the second logic level using the second switching logic.

11. The power stage circuit of claim 10 , wherein the controller is configured to trigger a second low-impedance state of the second switch on a subsequent fourth transition of the PWM signal from the second logic level to the first logic level using the second switching logic;
wherein, in response to the second low-impedance state of the second switch after the fourth transition, the controller is configured to:
receive a negative maximum current limit indication from the current comparator in response to current of the output violating a maximum negative current limit;
command a second high-impedance state of the second switch in response to the negative maximum current limit indication using the second switching logic; and
command a second low-impedance state of the first switch in response to the negative current limit indication using the second switching logic.

12. The power stage circuit of claim 1 , wherein the controller is configured to:
trigger a second high-impedance state of the second switch on a fourth transition of the PWM signal from the first logic level to the second logic level using the second switching logic;
initiate a second non-overlapping interval in response to the fourth transition using the second switching logic;
receive a second body diode conduction indication of the second switch during the second non-overlapping interval from a second body diode conduction sensor coupled across the second power transistor

Assignees

• Analog Devices International Unlimited Co

Inventors

• Chao Hio Leong

Classifications

• H02M1/0077

  Plural converter units whose outputs are connected in series · CPC title

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title

• H02M3/1566

  with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title

• H02M1/327

  against abnormal temperatures · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title