Trench semiconductor device having multiple active trench depths and method

Patent metadata

Field	Value
Publication number	US-10847660-B2
Application number	US-201916546049-A
Country	US
Kind code	B2
Filing date	Aug 20, 2019
Priority date	Mar 6, 2015
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A method of forming a semiconductor device includes providing a region of semiconductor material comprising a major surface. A termination trench is provided extending from a first portion of the major surface into the region of semiconductor material to a first depth and has a first width. A first active trench is provided extending from a second portion of the major surface into the region of semiconductor material to a second depth and has a second width less than the first width. A second active trench is provided extending from a third portion of the major surface into the region of semiconductor material to a third depth and has a third width less than the first width. A first conductive material is provided adjoining a fourth portion of the major surface, which is configured as a Schottky barrier. The selected trench depth difference alone or in combination with other features provides a semiconductor device having improved performance characteristics.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a region of semiconductor material comprising a major surface;
providing a termination trench extending from a first portion of the major surface into the region of semiconductor material to a first depth, wherein the termination trench has a first width;
providing a first active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein the first active trench has a second width less than the first width;
providing a second active trench extending from a third portion of the major surface into the region of semiconductor material to a third depth, wherein:
the second active trench has a third width less than the first width,
the third depth is greater than the second depth, and
the first active trench is interposed between the termination trench and the second active trench in a cross-sectional view;

providing a first conductive material adjoining a fourth portion of the major surface, wherein the first conductive material is configured to provide a Schottky barrier; and
providing a second conductive material in the first active trench separated from the region of semiconductor material by a first dielectric structure; and
providing a third conductive material in the second active trench separated from the region of semiconductor material by a second dielectric structure.

2. The method of claim 1 , wherein:
providing the termination trench and providing the first active trench comprises forming the termination trench and the first active trench in a single removal step, wherein:
the first depth is greater than the second depth to provide a trench depth difference; and
the trench depth difference is greater than zero and less than approximately 3.0 microns.

3. The method of claim 1 , wherein:
providing the termination trench and providing the first active trench includes providing a first width to third width ratio less than or equal to approximately 0.03.

4. The method of claim 1 , wherein:
providing the termination trench comprises forming the termination trench at an edge of the semiconductor device such that the termination trench is an outermost trench for the semiconductor device.

5. The method of claim 1 , wherein:
providing the second dielectric structure includes providing the second dielectric structure having a different thickness than that of the first dielectric structure.

6. A method of forming a semiconductor device comprising:
providing a region of semiconductor material having a first conductivity type and a major surface;
providing a termination trench extending from a first portion of the major surface into the region of semiconductor material to a first depth, the termination trench having a first width, wherein the termination trench is disposed at an edge of the semiconductor device such that the termination trench is an outermost trench for the semiconductor device;
providing a first active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein the first active trench has a second width;
providing a second active trench extending from a third portion of the major surface into the region of semiconductor material to a third depth, wherein the second active trench has a third width, and wherein the third depth is greater than the second depth, wherein:
the termination trench is laterally interposed between the edge and the first active trench and the second active trench;
the first active trench is interposed between the second active trench and the termination trench;
the first depth is greater than the second depth; and
the first width is greater than the second width and the third width;

providing a first conductive material within the first active trench and separated from the region of semiconductor material by a first dielectric region;
providing a second conductive material within the second active trench and separated from the region of semiconductor material by a second dielectric region; and
providing a third conductive material adjoining a fourth portion of the major surface, wherein the third conductive material is configured to provide a Schottky barrier.

7. The method of claim 6 , wherein:
providing the termination trench and providing the first active trench comprises providing the termination trench and the first active trench in a single removal step.

8. The method of claim 6 , further comprising:
providing a conductive spacer disposed along a sidewall of the termination trench and separated from the region of semiconductor material by a third dielectric region that adjoins the sidewall surface and a lower surface of the termination trench; and
providing a dielectric layer disposed adjacent to the conductive spacer within the termination trench such that the conductive spacer is laterally interposed between the dielectric layer and the third dielectric region, wherein:
the first depth is greater than the second depth in a range greater than zero to approximately 3.0 microns; and
the third conductive material physically contacts the conductive spacer.

9. The method of claim 6 , wherein:
providing the first active trench comprises providing a plurality of first active trenches each having the second depth;
providing the second active trench comprises providing a plurality of second active trenches where at least two of the second active trenches have the third depth;
one of the plurality of first active trenches is interposed between an outermost one of the plurality of second active trenches and the termination trench in a cross-sectional view; and
another one of the plurality of first active trenches is interposed between a pair of second active trenches in the cross-sectional view.

10. The method of claim 6 , further comprising:
providing a third active trench extending from a fifth portion of the major surface to the second depth; and
providing a fourth conductive material within the third active trench and separated from the region of semiconductor material by a third dielectric region; wherein:
the third width is different than the second width; and
the second active trench is interposed between the first active trench and the third active trench in a cross-sectional view such that the second active trench is closer to the edge of the semiconductor device than the third active trench.

11. The method of claim 6 , wherein:
providing the termination trench and providing the first active trench comprises providing a second width to first width ratio in a range from approximately 0.005 to approximately 0.125.

12. The method of claim 6 , wherein:
providing the region of semiconductor material comprises providing a semiconductor substrate having a semiconductor layer adjoining a surface of the semiconductor substrate, wherein the semiconductor layer has a non-uniform dopant profile.

13. The method of claim 6 further comprising:
providing a doped layer adjoining the fourth portion of the major surface proximate to the third conductive material, wherein the doped layer has a fourth depth less than the second depth.

14. A method of forming a semiconductor device, comprising:
providing a region of semiconductor material comprising a semiconductor layer adjoining a semiconductor substrate, the semiconductor layer defining a major surface, wherein the semiconductor layer has a first dopant concentration and the semiconductor substrate has a second dopant concentration different than the first dopant concentr

Assignees

• Semiconductor Components Ind Llc

Inventors

• Quddus Mohammed Tanvir
• Mudholkar Mihir
• Thomason Michael

Classifications

• H10D8/051

  of Schottky diodes · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D62/60

  Impurity distributions or concentrations · CPC title