Gallium nitride transistor with improved termination structure

Patent metadata

Field	Value
Publication number	US-10847644-B2
Application number	US-201916391731-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Apr 23, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A gallium nitride transistor includes one or more P-type hole injection structures that are positioned between the gate and the drain. The P-type hole injection structures are configured to inject holes in the transistor channel to combine with trapped carriers (e.g., electrons) so the electrical conductivity of the channel is less susceptible to previous voltage potentials applied to the transistor.

First claim

What is claimed is:

1. A transistor comprising:
a semiconductor substrate;
a source region formed in the substrate and including a source electrode in contact with a portion of the substrate;
a drain region formed in the substrate and separated from the source region;
a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region;
a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region;
a dielectric layer formed over and in contact with a first portion of the P-type layer; and
a continuous metal layer made from a uniform material that is (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in direct contact with a second portion of the P-type layer to form a hole injection electrode, and (3) formed over and in contact with a portion of the dielectric layer to form a field plate for the hole injection region.

2. The transistor of claim 1 wherein the continuous metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer.

3. The transistor of claim 2 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across a second region of the top surface of the P-type layer.

4. The transistor of claim 3 wherein the field plate extends across the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer.

5. The transistor of claim 1 wherein the continuous metal layer is in ohmic contact with the P-type layer.

6. The transistor of claim 1 further comprising a plurality of individual hole injection regions formed along a length of the drain region.

7. The transistor of claim 1 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region.

8. The transistor of claim 7 wherein the second hole injection region includes a P-type layer that is in contact with a portion of the substrate and is not in ohmic contact with the continuous metal layer.

9. The transistor of claim 1 wherein the continuous metal layer is formed over approximately one half of a top surface of the P-type layer and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer.

10. The transistor of claim 1 wherein the semiconductor substrate comprises gallium nitride.

11. A transistor comprising:
a semiconductor substrate;
a source region formed in the substrate and including a source electrode in contact with a portion of the substrate;
a drain region formed in the substrate and separated from the source region;
a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region;
a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region;
a dielectric layer extending across a first region of a top surface of the P-type layer; and
a metal layer that (1) extends across a drain region of the substrate to form a drain electrode, (2) abuts a first side surface of the P-type layer and is in direct contact with a second region of the top surface of the P-type layer to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate.

12. The transistor of claim 11 wherein the field plate is a hole injection region field plate.

13. The transistor of claim 12 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer.

14. The transistor of claim 13 wherein the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer.

15. The transistor of claim 11 wherein the metal layer is in ohmic contact with the P-type layer.

16. The transistor of claim 11 further comprising a plurality of individual hole injection regions formed along a length of the drain region.

17. The transistor of claim 11 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region.

18. The transistor of claim 17 wherein the second hole injection region includes a P-type layer that is in contact with a portion of the substrate and is not in ohmic contact with the continuous metal layer.

Assignees

• Navitas Semiconductor Inc
• Navitas Semiconductor Ltd

Inventors

• Kinzer Daniel M
• Hamdan Maher J

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title